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| author | Aurelien Jarno <aurelien@aurel32.net> | 2022-10-03 23:46:11 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2022-10-03 23:46:11 +0200 |
| commit | 3c0c78afabfed4b6fc161c159e628fbf14ff370b (patch) | |
| tree | c8dafc90670cbdc7cf4061477cee1671f31f6476 /sysdeps/x86 | |
| parent | e3e7fab7fe5186d18ca2046d99ba321c27db30ad (diff) | |
| download | glibc-3c0c78afabfed4b6fc161c159e628fbf14ff370b.tar.gz glibc-3c0c78afabfed4b6fc161c159e628fbf14ff370b.tar.xz glibc-3c0c78afabfed4b6fc161c159e628fbf14ff370b.zip | |
x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation
The AVX2 memrchr implementation uses the 'shlxl' instruction, which
belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which
belongs to the LZCNT CPU feature.
Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S")
Partially resolves: BZ #29611
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
Diffstat (limited to 'sysdeps/x86')
| -rw-r--r-- | sysdeps/x86/isa-level.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index 3c4480aba7..bbb90f5c5e 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -80,6 +80,7 @@ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 +#define LZCNT_X86_ISA_LEVEL 3 #define MOVBE_X86_ISA_LEVEL 3 /* ISA level >= 2 guaranteed includes. */ |