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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:22:26 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:22:26 +0300 |
| commit | c10b9b13f7471b08273effc8cd7e51b119df9348 (patch) | |
| tree | ca058c3446a247a5bccea211bd84a9c0130e1388 /sysdeps/x86 | |
| parent | 1663be053d50c06bb0f971c87d41a7b83f96fe15 (diff) | |
| download | glibc-c10b9b13f7471b08273effc8cd7e51b119df9348.tar.gz glibc-c10b9b13f7471b08273effc8cd7e51b119df9348.tar.xz glibc-c10b9b13f7471b08273effc8cd7e51b119df9348.zip | |
Vector pow for x86_64 and tests.
Here is implementation of vectorized pow containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for pow.
* math/bits/mathcalls.h: Added pow declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for pow.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: Added 2 argument wrappers.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector pow test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector pow.
Diffstat (limited to 'sysdeps/x86')
| -rw-r--r-- | sysdeps/x86/fpu/bits/math-vector.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h index 3b7158952c..a5317b9e32 100644 --- a/sysdeps/x86/fpu/bits/math-vector.h +++ b/sysdeps/x86/fpu/bits/math-vector.h @@ -44,6 +44,8 @@ # define __DECL_SIMD_exp __DECL_SIMD_x86_64 # undef __DECL_SIMD_expf # define __DECL_SIMD_expf __DECL_SIMD_x86_64 +# undef __DECL_SIMD_pow +# define __DECL_SIMD_pow __DECL_SIMD_x86_64 /* Workaround to exclude unnecessary symbol aliases in libmvec while GCC creates the vector names based on scalar asm name. @@ -65,6 +67,10 @@ __asm__ ("_ZGVbN4v___expf_finite = _ZGVbN4v_expf"); __asm__ ("_ZGVcN8v___expf_finite = _ZGVcN8v_expf"); __asm__ ("_ZGVdN8v___expf_finite = _ZGVdN8v_expf"); __asm__ ("_ZGVeN16v___expf_finite = _ZGVeN16v_expf"); +__asm__ ("_ZGVbN2vv___pow_finite = _ZGVbN2vv_pow"); +__asm__ ("_ZGVcN4vv___pow_finite = _ZGVcN4vv_pow"); +__asm__ ("_ZGVdN4vv___pow_finite = _ZGVdN4vv_pow"); +__asm__ ("_ZGVeN8vv___pow_finite = _ZGVeN8vv_pow"); # endif #endif |