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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 10:54:20 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 10:54:32 -0700 |
| commit | 1af30adcd59fae929371d3a56b239861b1088a6e (patch) | |
| tree | c8f904764ad403e83910455fd229a092db003b74 /sysdeps/x86 | |
| parent | 7c67e6e8b9815d18f548f9c54444adaef17c0a6e (diff) | |
| download | glibc-1af30adcd59fae929371d3a56b239861b1088a6e.tar.gz glibc-1af30adcd59fae929371d3a56b239861b1088a6e.tar.xz glibc-1af30adcd59fae929371d3a56b239861b1088a6e.zip | |
Initial Fast Short REP MOVSB (FSRM) support
The newer Intel processors support Fast Short REP MOVSB which has a feature bit in CPUID. This patch adds the Fast Short REP MOVSB (FSRM) bit to x86 cpu-features. * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. (index_cpu_FSRM): Likewise. (reg_FSRM): Likewise.
Diffstat (limited to 'sysdeps/x86')
| -rw-r--r-- | sysdeps/x86/cpu-features.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index c60c2e4eeb..2088bd73ee 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -76,6 +76,7 @@ #define bit_cpu_AVX512VL (1u << 31) #define bit_cpu_IBT (1u << 20) #define bit_cpu_SHSTK (1u << 7) +#define bit_cpu_FSRM (1 << 4) /* XCR0 Feature flags. */ #define bit_XMM_state (1 << 1) @@ -207,6 +208,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_cpu_POPCNT COMMON_CPUID_INDEX_1 # define index_cpu_IBT COMMON_CPUID_INDEX_7 # define index_cpu_SHSTK COMMON_CPUID_INDEX_7 +# define index_cpu_FSRM COMMON_CPUID_INDEX_7 # define reg_CX8 edx # define reg_CMOV edx @@ -238,6 +240,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define reg_POPCNT ecx # define reg_IBT edx # define reg_SHSTK ecx +# define reg_FSRM edx # define index_arch_Fast_Rep_String FEATURE_INDEX_1 # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1 |