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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-10-08 08:19:15 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-10-09 11:52:30 -0700 |
| commit | 7674695cf7e28528be7243ceb30c9a600bbaa7b5 (patch) | |
| tree | 4cac579b2110239b2adcf0336b6fb760c92644cc /sysdeps/x86/sys | |
| parent | bb5fd5ce64b598085bdb8a05cb53777480fe093c (diff) | |
| download | glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.tar.gz glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.tar.xz glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.zip | |
<sys/platform/x86.h>: Add Intel UINTR support
Add Intel UINTR support to <sys/platform/x86.h>.
Diffstat (limited to 'sysdeps/x86/sys')
| -rw-r--r-- | sysdeps/x86/sys/platform/x86.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h index 2ba6d3c4f2..22bb28449d 100644 --- a/sysdeps/x86/sys/platform/x86.h +++ b/sysdeps/x86/sys/platform/x86.h @@ -241,7 +241,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define bit_cpu_AVX512_4VNNIW (1u << 2) #define bit_cpu_AVX512_4FMAPS (1u << 3) #define bit_cpu_FSRM (1u << 4) -#define bit_cpu_INDEX_7_EDX_5 (1u << 5) +#define bit_cpu_UINTR (1u << 5) #define bit_cpu_INDEX_7_EDX_6 (1u << 6) #define bit_cpu_INDEX_7_EDX_7 (1u << 7) #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) @@ -460,7 +460,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7 #define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7 #define index_cpu_FSRM COMMON_CPUID_INDEX_7 -#define index_cpu_INDEX_7_EDX_5 COMMON_CPUID_INDEX_7 +#define index_cpu_UINTR COMMON_CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_6 COMMON_CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_7 COMMON_CPUID_INDEX_7 #define index_cpu_AVX512_VP2INTERSECT COMMON_CPUID_INDEX_7 @@ -679,7 +679,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define reg_AVX512_4VNNIW edx #define reg_AVX512_4FMAPS edx #define reg_FSRM edx -#define reg_INDEX_7_EDX_5 edx +#define reg_UINTR edx #define reg_INDEX_7_EDX_6 edx #define reg_INDEX_7_EDX_7 edx #define reg_AVX512_VP2INTERSECT edx |