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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2020-08-28 17:51:40 +0100 |
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| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2020-10-14 17:29:12 +0100 |
| commit | b915da29dab5d8c6b9cdb1ee6fdc1e0ec6ef39e1 (patch) | |
| tree | 5f060261fc04bcfe189333dfbc315c78285d005e /sysdeps/x86/nptl | |
| parent | 4bd28df0b0598c380f4ae63b96eaadc782c9d709 (diff) | |
| download | glibc-b915da29dab5d8c6b9cdb1ee6fdc1e0ec6ef39e1.tar.gz glibc-b915da29dab5d8c6b9cdb1ee6fdc1e0ec6ef39e1.tar.xz glibc-b915da29dab5d8c6b9cdb1ee6fdc1e0ec6ef39e1.zip | |
AArch64: Improve backwards memmove performance
On some microarchitectures performance of the backwards memmove improves if the stores use STR with decreasing addresses. So change the memmove loop in memcpy_advsimd.S to use 2x STR rather than STP. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> (cherry picked from commit bd394d131c10c9ec22c6424197b79410042eed99)
Diffstat (limited to 'sysdeps/x86/nptl')
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