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| author | Aurelien Jarno <aurelien@aurel32.net> | 2022-10-03 23:46:11 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2022-10-03 23:46:11 +0200 |
| commit | 7e8283170c5d6805b609a040801d819e362a6292 (patch) | |
| tree | faabe13505d48c0b933f175b088794beb9028072 /sysdeps/x86/isa-level.h | |
| parent | 3c0c78afabfed4b6fc161c159e628fbf14ff370b (diff) | |
| download | glibc-7e8283170c5d6805b609a040801d819e362a6292.tar.gz glibc-7e8283170c5d6805b609a040801d819e362a6292.tar.xz glibc-7e8283170c5d6805b609a040801d819e362a6292.zip | |
x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr implementations
The AVX2 strrchr and wcsrchr implementation uses the 'blsmsk'
instruction which belongs to the BMI1 CPU feature and the 'shrx'
instruction, which belongs to the BMI2 CPU feature.
Fixes: df7e295d18ff ("x86: Optimize {str|wcs}rchr-avx2")
Partially resolves: BZ #29611
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
Diffstat (limited to 'sysdeps/x86/isa-level.h')
| -rw-r--r-- | sysdeps/x86/isa-level.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index bbb90f5c5e..06f6c9663e 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -79,6 +79,7 @@ /* ISA level >= 3 guaranteed includes. */ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 +#define BMI1_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 #define LZCNT_X86_ISA_LEVEL 3 #define MOVBE_X86_ISA_LEVEL 3 |