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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 15:58:05 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 15:58:05 +0300 |
| commit | 9c02f663f6b387b3905b629ffe584c9abf2030dc (patch) | |
| tree | 587a88eca7b4c3abd7c5482c07c7a35778025785 /sysdeps/x86/fpu | |
| parent | 774488f88aeed6b838fe29c3c7561433c242a3c9 (diff) | |
| download | glibc-9c02f663f6b387b3905b629ffe584c9abf2030dc.tar.gz glibc-9c02f663f6b387b3905b629ffe584c9abf2030dc.tar.xz glibc-9c02f663f6b387b3905b629ffe584c9abf2030dc.zip | |
Vector exp for x86_64 and tests.
Here is implementation of vectorized exp containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for exp.
* math/bits/mathcalls.h: Added exp declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for exp.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector exp test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector exp.
Diffstat (limited to 'sysdeps/x86/fpu')
| -rw-r--r-- | sysdeps/x86/fpu/bits/math-vector.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h index 5c3e492ef9..9a353bc62a 100644 --- a/sysdeps/x86/fpu/bits/math-vector.h +++ b/sysdeps/x86/fpu/bits/math-vector.h @@ -40,6 +40,8 @@ # define __DECL_SIMD_log __DECL_SIMD_x86_64 # undef __DECL_SIMD_logf # define __DECL_SIMD_logf __DECL_SIMD_x86_64 +# undef __DECL_SIMD_exp +# define __DECL_SIMD_exp __DECL_SIMD_x86_64 /* Workaround to exclude unnecessary symbol aliases in libmvec while GCC creates the vector names based on scalar asm name. @@ -53,6 +55,10 @@ __asm__ ("_ZGVbN4v___logf_finite = _ZGVbN4v_logf"); __asm__ ("_ZGVcN8v___logf_finite = _ZGVcN8v_logf"); __asm__ ("_ZGVdN8v___logf_finite = _ZGVdN8v_logf"); __asm__ ("_ZGVeN16v___logf_finite = _ZGVeN16v_logf"); +__asm__ ("_ZGVbN2v___exp_finite = _ZGVbN2v_exp"); +__asm__ ("_ZGVcN4v___exp_finite = _ZGVcN4v_exp"); +__asm__ ("_ZGVdN4v___exp_finite = _ZGVdN4v_exp"); +__asm__ ("_ZGVeN8v___exp_finite = _ZGVeN8v_exp"); # endif #endif |