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author | H.J. Lu <hjl.tools@gmail.com> | 2020-07-06 11:48:09 -0700 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2020-07-06 11:48:42 -0700 |
commit | 3f4b61a0b8de67ef9f20737919c713ddfc4bd620 (patch) | |
tree | 521cfbc4f297a2fe5d4fc91e6c30d590f1225027 /sysdeps/x86/dl-tunables.list | |
parent | 6c010c5dde1735f93cc3a6597cdcc2b482af85f8 (diff) | |
download | glibc-3f4b61a0b8de67ef9f20737919c713ddfc4bd620.tar.gz glibc-3f4b61a0b8de67ef9f20737919c713ddfc4bd620.tar.xz glibc-3f4b61a0b8de67ef9f20737919c713ddfc4bd620.zip |
x86: Add thresholds for "rep movsb/stosb" to tunables
Add x86_rep_movsb_threshold and x86_rep_stosb_threshold to tunables to update thresholds for "rep movsb" and "rep stosb" at run-time. Note that the user specified threshold for "rep movsb" smaller than the minimum threshold will be ignored. Reviewed-by: Carlos O'Donell <carlos@redhat.com>
Diffstat (limited to 'sysdeps/x86/dl-tunables.list')
-rw-r--r-- | sysdeps/x86/dl-tunables.list | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/sysdeps/x86/dl-tunables.list b/sysdeps/x86/dl-tunables.list index 251b926ce4..1a4a93a070 100644 --- a/sysdeps/x86/dl-tunables.list +++ b/sysdeps/x86/dl-tunables.list @@ -30,6 +30,30 @@ glibc { x86_non_temporal_threshold { type: SIZE_T } + x86_rep_movsb_threshold { + type: SIZE_T + # Since there is overhead to set up REP MOVSB operation, REP MOVSB + # isn't faster on short data. The memcpy micro benchmark in glibc + # shows that 2KB is the approximate value above which REP MOVSB + # becomes faster than SSE2 optimization on processors with Enhanced + # REP MOVSB. Since larger register size can move more data with a + # single load and store, the threshold is higher with larger register + # size. Note: Since the REP MOVSB threshold must be greater than 8 + # times of vector size, the minium value must be updated at run-time. + minval: 1 + default: 2048 + } + x86_rep_stosb_threshold { + type: SIZE_T + # Since there is overhead to set up REP STOSB operation, REP STOSB + # isn't faster on short data. The memset micro benchmark in glibc + # shows that 2KB is the approximate value above which REP STOSB + # becomes faster on processors with Enhanced REP STOSB. Since the + # stored value is fixed, larger register size has minimal impact + # on threshold. + minval: 1 + default: 2048 + } x86_data_cache_size { type: SIZE_T } |