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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-05-21 13:36:54 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-05-21 13:36:54 -0700 |
| commit | 76d5b2f002a1243ddba06bd646249553353f4322 (patch) | |
| tree | a9db4dc91431e7443ad8d64ffed5e4437c33f62e /sysdeps/x86/cpu-features.c | |
| parent | 03acbc1f71800a34dfbf4371c3443b1f1c73a4b9 (diff) | |
| download | glibc-76d5b2f002a1243ddba06bd646249553353f4322.tar.gz glibc-76d5b2f002a1243ddba06bd646249553353f4322.tar.xz glibc-76d5b2f002a1243ddba06bd646249553353f4322.zip | |
x86: Update Intel Atom processor family optimization
Enable Intel Silvermont optimization for Intel Goldmont Plus. Detect more Intel Airmont processors. Optimize Intel Tremont like Intel Silvermont with rep string instructions.
Diffstat (limited to 'sysdeps/x86/cpu-features.c')
| -rw-r--r-- | sysdeps/x86/cpu-features.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index b6d5d9d4b1..916bbf5242 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -347,18 +347,23 @@ init_cpu_features (struct cpu_features *cpu_features) case 0x57: /* Knights Landing. Enable Silvermont optimizations. */ + case 0x7a: + /* Unaligned load versions are faster than SSSE3 + on Goldmont Plus. */ + case 0x5c: case 0x5f: /* Unaligned load versions are faster than SSSE3 on Goldmont. */ case 0x4c: + case 0x5a: + case 0x75: /* Airmont is a die shrink of Silvermont. */ case 0x37: case 0x4a: case 0x4d: - case 0x5a: case 0x5d: /* Unaligned load versions are faster than SSSE3 on Silvermont. */ @@ -369,6 +374,19 @@ init_cpu_features (struct cpu_features *cpu_features) | bit_arch_Slow_SSE4_2); break; + case 0x86: + case 0x96: + case 0x9c: + /* Enable rep string instructions, unaligned load, unaligned + copy, pminub and avoid SSE 4.2 on Tremont. */ + cpu_features->feature[index_arch_Fast_Rep_String] + |= (bit_arch_Fast_Rep_String + | bit_arch_Fast_Unaligned_Load + | bit_arch_Fast_Unaligned_Copy + | bit_arch_Prefer_PMINUB_for_stringop + | bit_arch_Slow_SSE4_2); + break; + default: /* Unknown family 0x06 processors. Assuming this is one of Core i3/i5/i7 processors if AVX is available. */ |