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authorUlrich Drepper <drepper@redhat.com>2009-07-23 13:42:46 -0700
committerUlrich Drepper <drepper@redhat.com>2009-07-23 13:42:46 -0700
commit3e9099b4f6666cd05b62d2829f65161daddb151b (patch)
tree91be21d2342e432272c8f5429f3ae7eb2a76fbfa /sysdeps/unix
parentd28797e426aa7e4e380a7ae10faf4aa3c4767e0b (diff)
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Add more cache descriptors for L3 caches on x86 and x86-64.
The most recent AP 485 describes a few more cache descriptors for
L3 caches with 24-way associativity.
Diffstat (limited to 'sysdeps/unix')
-rw-r--r--sysdeps/unix/sysv/linux/i386/sysconf.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/unix/sysv/linux/i386/sysconf.c b/sysdeps/unix/sysv/linux/i386/sysconf.c
index efe1a639cd..ff3cf9f7c7 100644
--- a/sysdeps/unix/sysv/linux/i386/sysconf.c
+++ b/sysdeps/unix/sysv/linux/i386/sysconf.c
@@ -138,6 +138,9 @@ static const struct intel_02_cache_info
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
     { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
     { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
+    { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
+    { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
+    { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
   };
 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))