Update.

2004-01-14  Steven Munroe  <sjmunroe@us.ibm.com>

	* include/libc-symbols.h [HAVE_ASM_GLOBAL_DOT_NAME]
	(_symbol_version): Use C_SYMBOL_DOT_NAME to create '.'ed symbols.
	(_default_symbol_version): Use C_SYMBOL_DOT_NAME to create '.'ed
	symbols.
	* sysdeps/powerpc/Makefile: Add rtld-global-offsets.sym to
	gen-as-const-headers.
	* sysdeps/powerpc/elf/rtld-global-offsets.sym: New file.
	* sysdeps/powerpc/sysdep.h: Define v# symbols for vector registers.
	Define PPC_FEATURE_* masks for Aux Vector AT_HWCAP.
	* sysdeps/unix/sysv/linux/kernel-features.h
	(__ASSUME_SWAPCONTEXT_SYSCALL): Define for PPC and 2.6.0 kernels.
	* sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h [!__WORDSIZE == 32]:
	Declare mcontext_t inline and include altivec state for 64-bit.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions: Add GLIBC_2.3.4
	versions for setcontext, getcontext, and swapcontext.

	* sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions: Add GLIBC_2.3.4
	versions for setcontext, getcontext, swapcontext, and makecontext.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S
	(__getcontext):  Upgrade to save Altivec regs and version GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)](__novec_getcontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/makecontext.S
	(__makecontext): Use parm save area instead of compiler_dw to hold
	context pointer.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
	(__setcontext):  Upgrade to restore Altivec regs and version
	GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)](__novec_setcontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
	(__swapcontext): Upgrade to swap Altivec regs and version GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)](__novec_swapcontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h
	(SIGCONTEXT_V_REGS_PTR, SIGCONTEXT_V_RESERVE): Defined.


2004-01-12  Steven Munroe  <sjmunroe@us.ibm.com>

	* sysdeps/unix/sysv/linux/powerpc/powerpc32/Versions: Add GLIBC_2.3.4
	versions for setcontext, getcontext, swapcontext, and makecontext.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
	(__getcontext):  Upgrade to save Altivec regs and version GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)](__novec_getcontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/makecontext.S
	(__makecontext): Upgrade to align for Altivec regs and version
	GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)](__novec_makecontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
	(__setcontext):  Upgrade to restore Altivec regs and version
	GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)](__novec_setcontext):
	Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
	(__swapcontext): Upgrade to swap Altivec regs and version GLIBC_2_3_4.
	[SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)]
	(__novec_swapcontext): Compatible with GLIBC_2.3.3 release.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h:
	(_UC_VSCR, _UC_VRSAVE): Define.
	(_FRAME_BACKCHAIN, _FRAME_LR_SAVE,_FRAME_PARM_SAVE1,_FRAME_PARM_SAVE2,
	_FRAME_PARM_SAVE3, _FRAME_PARM_SAVE4): Defined.

1 files changed, 70 insertions, 4 deletions

diff --git a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
index b75e25a3c8..a499a80ef9 100644
--- a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
+++ b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc.
+/* Copyright (C) 1998, 1999, 2002, 2004 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -29,7 +29,7 @@
 #if __WORDSIZE == 32
 
 /* Number of general registers.  */
-#define NGREG	48
+# define NGREG	48
 
 /* Container for all general registers.  */
 typedef unsigned long gregset_t[NGREG];
@@ -62,8 +62,74 @@ typedef struct
 
 #else
 
-/* For 64-bit, a machine context is exactly a sigcontext.  */
-typedef struct sigcontext mcontext_t;
+/* For 64-bit kernels with Altivec support, a machine context is exactly 
+ * a sigcontext.  For older kernel (without Altivec) the sigcontext matches 
+ * the mcontext upto but not including the v_regs field.  For kernels that 
+ * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the 
+ * v_regs field may not exit and should not be referenced.  The v_regd field
+ * can be refernced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC
+ * is set in AT_HWCAP.  */
+    
+# include <asm/types.h>
+
+/* Number of general registers.  */
+# define NGREG	48	/* includes r0-r31, nip, msr, lr, etc.   */
+# define NFPREG	33	/* includes fp0-fp31 &fpscr.  */
+# define NVRREG	34	/* includes v0-v31, vscr, & vrsave in split vectors */
+
+typedef unsigned long gregset_t[NGREG];
+typedef double fpregset_t[NFPREG];
+
+/* Container for Altivec/VMX Vector Status and Control Register.  Only 32-bits
+   but can only be copied to/from a 128-bit vector register.  So we allocated 
+   a whole quadword speedup save/restore.  */
+typedef struct _libc_vscr
+{
+	unsigned int __pad[3];
+	unsigned int vscr_word;
+} vscr_t;
+
+/* Container for Altivec/VMX registers and status.
+   Must to be aligned on a 16-byte boundary. */
+typedef struct _libc_vrstate
+{
+	unsigned int	vrregs[32][4];
+	vscr_t		vscr;
+	unsigned int	vrsave;
+	unsigned int	__pad[3];
+} vrregset_t  __attribute__((__aligned__(16)));
+
+typedef struct {
+	unsigned long	__unused[4];
+	int		signal;
+	int		__pad0;
+	unsigned long	handler;
+	unsigned long	oldmask;
+	struct pt_regs	*regs;
+	gregset_t	gp_regs;
+	fpregset_t	fp_regs;
+/*
+ * To maintain compatibility with current implementations the sigcontext is 
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This 
+ * allows the array of vector registers to be quadword aligned independent of 
+ * the alignment of the containing sigcontext or ucontext. It is the 
+ * responsibility of the code setting the sigcontext to set this pointer to 
+ * either NULL (if this processor does not support the VMX feature) or the 
+ * address of the first quadword within the allocated (vmx_reserve) area.
+ *
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually  
+ * an array of 34 quadword entries.  The entries with 
+ * indexes 0-31 contain the corresponding vector registers.  The entry with 
+ * index 32 contains the vscr as the last word (offset 12) within the 
+ * quadword.  This allows the vscr to be stored as either a quadword (since 
+ * it must be copied via a vector register to/from storage) or as a word.  
+ * The entry with index 33 contains the vrsave as the first word (offset 0) 
+ * within the quadword.
+ */
+	vrregset_t	*v_regs;
+	long		vmx_reserve[NVRREG+NVRREG+1];
+} mcontext_t;
 
 #endif