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authorDavid S. Miller <davem@davemloft.net>2012-05-31 14:19:30 -0700
committerDavid S. Miller <davem@davemloft.net>2012-05-31 14:19:30 -0700
commitf230c29b40cc36ce62387664be92c3cf94119efe (patch)
tree26028666b279654830d54846e9194429accfd9f5 /sysdeps/sparc/sparc64/memset.S
parentfed806c3af7b6421e17ac50f8129dbe4fd693e4a (diff)
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Avoid performance penalty in sparc optimized memcpy/memset.
fmovd clears the current exception field in the %fsr, fsrc2
does not and therefore runs more efficiently on some cpus.

	* sysdeps/sparc/sparc64/memcpy.S: Use fsrc2 to move 64-bit
	values between float registers.
	* sysdeps/sparc/sparc64/memset.S: Likewise.
	* sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S: Likewise.
Diffstat (limited to 'sysdeps/sparc/sparc64/memset.S')
-rw-r--r--sysdeps/sparc/sparc64/memset.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/sysdeps/sparc/sparc64/memset.S b/sysdeps/sparc/sparc64/memset.S
index b9c52aa9d2..5e92936682 100644
--- a/sysdeps/sparc/sparc64/memset.S
+++ b/sysdeps/sparc/sparc64/memset.S
@@ -109,16 +109,16 @@ ENTRY(memset)
 	membar		#StoreStore | #LoadStore
 	andcc		%o3, 0xc0, %g5
 	and		%o2, 0x3f, %o2
-	fmovd		%f0, %f2
-	fmovd		%f0, %f4
+	fsrc2		%f0, %f2
+	fsrc2		%f0, %f4
 	andn		%o3, 0xff, %o3
-	fmovd		%f0, %f6
+	fsrc2		%f0, %f6
 	cmp		%g5, 64
-	fmovd		%f0, %f8
-	fmovd		%f0, %f10
-	fmovd		%f0, %f12
+	fsrc2		%f0, %f8
+	fsrc2		%f0, %f10
+	fsrc2		%f0, %f12
 	brz,pn		%g5, 10f
-	 fmovd		%f0, %f14
+	 fsrc2		%f0, %f14
 	be,pn		%icc, 2f
 	 stda		%f0, [%o0 + 0x00] %asi
 	cmp		%g5, 128