Add more sparc VIS3 optimized math routines.

	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file.
	* sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines.

	* sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies:
	New file.

1 files changed, 79 insertions, 0 deletions

diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S
new file mode 100644
index 0000000000..d7e5d24c17
--- /dev/null
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S
@@ -0,0 +1,79 @@
+/* floor function, sparc32 v9 vis3 version.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+
+	/* Since changing the rounding mode is extremely expensive, we
+	   try to round up using a method that is rounding mode
+	   agnostic.
+
+	   We add then subtract (or subtract than add if the initial
+	   value was negative) 2**23 to the value, then subtract it
+	   back out.
+
+	   This will clear out the fractional portion of the value.
+	   One of two things will happen for non-whole initial values.
+	   Either the rounding mode will round it up, or it will be
+	   rounded down.  If the value started out whole, it will be
+	   equal after the addition and subtraction.  This means we
+	   can accurately detect with one test whether we need to add
+	   another 1.0 to round it up properly.
+
+	   VIS instructions are used to facilitate the formation of
+	   easier constants, and the propagation of the sign bit.  */
+
+#define TWO_FIFTYTWO	0x43300000		/* 2**52 */
+#define ONE_DOT_ZERO	0x3ff00000		/* 1.0 */
+
+#define ZERO		%f10			/* 0.0 */
+#define SIGN_BIT	%f12			/* -0.0 */
+
+ENTRY (__floor_vis3)
+	sethi	%hi(TWO_FIFTYTWO), %o2
+	sllx	%o0, 32, %o0
+	sethi	%hi(ONE_DOT_ZERO), %o3
+	or	%o0, %o1, %o0
+	movxtod	%o0, %f0
+	sllx	%o2, 32, %o2
+	fzero	ZERO
+	sllx	%o3, 32, %o3
+
+	fnegd	ZERO, SIGN_BIT
+
+	stx	%o2, [%sp + 72]
+	fabsd	%f0, %f14
+
+	ldd	[%sp + 72], %f16
+	fcmpd	%fcc3, %f14, %f16
+
+	fmovduge %fcc3, ZERO, %f16
+	fand	%f0, SIGN_BIT, SIGN_BIT
+
+	for	%f16, SIGN_BIT, %f16
+	faddd	%f0, %f16, %f18
+	fsubd	%f18, %f16, %f18
+	fcmpd	%fcc2, %f18, %f0
+	movxtod	%o3, %f20
+
+	fmovdule %fcc2, ZERO, %f20
+	fsubd	%f18, %f20, %f0
+	fabsd	%f0, %f0
+	retl
+	 for	%f0, SIGN_BIT, %f0
+END (__floor_vis3)