Create a header for sparc ifunc expansion and use it for VIS3 ifuncs.

	* sysdeps/sparc/sparc-ifunc.h: New file.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: Use sparc-ifunc.h
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmax.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaxf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmin.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fminf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_fmax.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_fmaxf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_fmin.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_fminf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S: Likewise.
	* sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S: Likewise.

1 files changed, 112 insertions, 0 deletions

diff --git a/sysdeps/sparc/sparc-ifunc.h b/sysdeps/sparc/sparc-ifunc.h
new file mode 100644
index 0000000000..db53a7126e
--- /dev/null
+++ b/sysdeps/sparc/sparc-ifunc.h
@@ -0,0 +1,112 @@
+/* This file is part of the GNU C Library.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+
+#ifdef __ASSEMBLER__
+
+# ifdef SHARED
+
+#  define SPARC_ASM_IFUNC_DFLT(name, dflt)		\
+ENTRY (__##name)					\
+	.type	__##name, @gnu_indirect_function;	\
+	SETUP_PIC_REG_LEAF(o3, o5);			\
+	sethi	%gdop_hix22(dflt), %o1;			\
+	xor	%o1, %gdop_lox10(dflt), %o1;		\
+	add	%o3, %o1, %o1;				\
+	retl;						\
+	 mov	%o1, %o0;				\
+END (__##name)
+
+#  define SPARC_ASM_IFUNC1(name, m1, f1, dflt)		\
+ENTRY (__##name)					\
+	.type	__##name, @gnu_indirect_function;	\
+	SETUP_PIC_REG_LEAF(o3, o5);			\
+	set	m1, %o1;				\
+	andcc	%o0, %o1, %g0;				\
+	be	9f;					\
+	 nop;						\
+	sethi	%gdop_hix22(f1), %o1;			\
+	xor	%o1, %gdop_lox10(f1), %o1;		\
+	ba	10f;					\
+	 nop;						\
+9:	sethi	%gdop_hix22(dflt), %o1;			\
+	xor	%o1, %gdop_lox10(dflt), %o1;		\
+10:	add	%o3, %o1, %o1;				\
+	retl;						\
+	 mov	%o1, %o0;				\
+END (__##name)
+
+# else /* SHARED */
+
+# ifdef __arch64__
+#  define SET(SYM, TMP, REG)	setx SYM, TMP, REG
+# else
+#  define SET(SYM, TMP, REG)	set SYM, REG
+# endif
+
+#  define SPARC_ASM_IFUNC_DFLT(name, dflt)		\
+ENTRY (__##name)					\
+	.type	__##name, @gnu_indirect_function;	\
+	SET(dflt, %g1, %o1);				\
+	retl;						\
+	 mov	%o1, %o0;				\
+END (__##name)
+
+#  define SPARC_ASM_IFUNC1(name, m1, f1, dflt)		\
+ENTRY (__##name)					\
+	.type	__##name, @gnu_indirect_function;	\
+	set	m1, %o1;				\
+	andcc	%o0, %o1, %g0;				\
+	be	9f;					\
+	 nop;						\
+	SET(f1, %g1, %o1);				\
+	ba	10f;					\
+	 nop;						\
+9:	SET(dflt, %g1, %o1);				\
+10:	retl;						\
+	 mov	%o1, %o0;				\
+END (__##name)
+
+# endif /* SHARED */
+
+# ifdef HAVE_AS_VIS3_SUPPORT
+
+#define SPARC_ASM_VIS3_IFUNC(name)			\
+	SPARC_ASM_IFUNC1(name, HWCAP_SPARC_VIS3,	\
+			 __##name##_vis3, __##name##_generic)
+
+# else /* HAVE_AS_VIS3_SUPPORT */
+
+#define SPARC_ASM_VIS3_IFUNC(name)			\
+	SPARC_ASM_IFUNC_DFLT(name, __##name##_generic)
+
+# endif /* HAVE_AS_VIS3_SUPPORT */
+
+
+#else	/* __ASSEMBLER__ */
+
+# define sparc_libm_ifunc(name, expr)					\
+  extern void *name##_ifunc (int) __asm__ (#name);			\
+  void *name##_ifunc (int hwcap)					\
+  {									\
+    __typeof (name) *res = expr;					\
+    return res;								\
+  }									\
+  __asm__ (".type " #name ", %gnu_indirect_function");
+
+#endif	/* __ASSEMBLER__ */