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author | Joseph Myers <joseph@codesourcery.com> | 2012-11-03 17:07:56 +0000 |
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committer | Joseph Myers <joseph@codesourcery.com> | 2012-11-03 17:07:56 +0000 |
commit | fbeafedeea37e0af1984a6511018d159f5ceed6a (patch) | |
tree | 3bca3c62f6c2004bf50708d4ced2500971a342b7 /sysdeps/s390/fpu | |
parent | 0244426b930b006b128ea0c874b1301e9528ad5f (diff) | |
download | glibc-fbeafedeea37e0af1984a6511018d159f5ceed6a.tar.gz glibc-fbeafedeea37e0af1984a6511018d159f5ceed6a.tar.xz glibc-fbeafedeea37e0af1984a6511018d159f5ceed6a.zip |
Make fenv.h FE_* macros usable in #if (bug 3439).
Diffstat (limited to 'sysdeps/s390/fpu')
-rw-r--r-- | sysdeps/s390/fpu/bits/fenv.h | 45 |
1 files changed, 27 insertions, 18 deletions
diff --git a/sysdeps/s390/fpu/bits/fenv.h b/sysdeps/s390/fpu/bits/fenv.h index 6df7b177f9..f6cc351231 100644 --- a/sysdeps/s390/fpu/bits/fenv.h +++ b/sysdeps/s390/fpu/bits/fenv.h @@ -24,16 +24,21 @@ of the appropriate bits in the FPU control word. */ enum { - FE_INVALID = 0x80, -#define FE_INVALID FE_INVALID - FE_DIVBYZERO = 0x40, -#define FE_DIVBYZERO FE_DIVBYZERO - FE_OVERFLOW = 0x20, -#define FE_OVERFLOW FE_OVERFLOW - FE_UNDERFLOW = 0x10, -#define FE_UNDERFLOW FE_UNDERFLOW - FE_INEXACT = 0x08 -#define FE_INEXACT FE_INEXACT + FE_INVALID = +#define FE_INVALID 0x80 + FE_INVALID, + FE_DIVBYZERO = +#define FE_DIVBYZERO 0x40 + FE_DIVBYZERO, + FE_OVERFLOW = +#define FE_OVERFLOW 0x20 + FE_OVERFLOW, + FE_UNDERFLOW = +#define FE_UNDERFLOW 0x10 + FE_UNDERFLOW, + FE_INEXACT = +#define FE_INEXACT 0x08 + FE_INEXACT }; /* We dont use the y bit of the DXC in the floating point control register as glibc has no FE encoding for fe inexact incremented @@ -48,14 +53,18 @@ enum enum { - FE_TONEAREST = 0, -#define FE_TONEAREST FE_TONEAREST - FE_DOWNWARD = 0x3, -#define FE_DOWNWARD FE_DOWNWARD - FE_UPWARD = 0x2, -#define FE_UPWARD FE_UPWARD - FE_TOWARDZERO = 0x1 -#define FE_TOWARDZERO FE_TOWARDZERO + FE_TONEAREST = +#define FE_TONEAREST 0 + FE_TONEAREST, + FE_DOWNWARD = +#define FE_DOWNWARD 0x3 + FE_DOWNWARD, + FE_UPWARD = +#define FE_UPWARD 0x2 + FE_UPWARD, + FE_TOWARDZERO = +#define FE_TOWARDZERO 0x1 + FE_TOWARDZERO }; |