S390: Do not set FE_INEXACT with feraiseexcept (FE_OWERFLOW|FE_UNDERFLOW).

On s390 feraiseexcept (FE_OVERFLOW|FE_UNDERFLOW) sets FE_INEXACT, too.
This patch uses z196 zarch load rounded instruction which can suppress
FE_INEXACT exception if gcc has z196 support in used configuration.
Otherwise FE_INEXACT flag is set as before. The gcc support is tested
in a new configure-check.

A comment in fsetexcptflg.c is corrected as new exceptions are not
executed with the next floating-point instruction if fpc is set with
_FPU_SETCW macro. It seems the comment was copied e.g. from
sysdeps/x86_64/fpu/fsetexcptflg.c file.

ChangeLog:

	* config.h.in (HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT):
	New undefine.
	* sysdeps/s390/configure.ac: Add test for z196 zarch support.
	* sysdeps/s390/configure: Regenerated.
	* sysdeps/s390/fpu/fraiseexcpt.c (__feraiseexcept): Use ledbra
	instruction for raising over-/underflow if z196 zarch is supported
	by default.
	* sysdeps/s390/fpu/fsetexcptflg.c (fesetexceptflag):
	Correct comment.

2 files changed, 38 insertions, 6 deletions

diff --git a/sysdeps/s390/fpu/fraiseexcpt.c b/sysdeps/s390/fpu/fraiseexcpt.c
index 92a1a7db68..ac6dfe7739 100644
--- a/sysdeps/s390/fpu/fraiseexcpt.c
+++ b/sysdeps/s390/fpu/fraiseexcpt.c
@@ -35,6 +35,23 @@ fexceptadd (float d, float e)
   __asm__ __volatile__ ("aebr %0,%1" : : "f" (d), "f" (e) );
 }
 
+#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
+static __inline__ void
+fexceptround (double e)
+{
+  float d;
+  /* Load rounded from double to float with M3 = round toward 0, M4 = Suppress
+     IEEE-inexact exception.
+     In case of e=0x1p128 and the overflow-mask bit is zero, only the
+     IEEE-overflow flag is set. If overflow-mask bit is one, DXC field is set to
+     0x20 "IEEE overflow, exact".
+     In case of e=0x1p-150 and the underflow-mask bit is zero, only the
+     IEEE-underflow flag is set. If underflow-mask bit is one, DXC field is set
+     to 0x10 "IEEE underflow, exact".
+     This instruction is available with a zarch machine >= z196.  */
+  __asm__ __volatile__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
+}
+#endif
 
 int
 __feraiseexcept (int excepts)
@@ -54,13 +71,29 @@ __feraiseexcept (int excepts)
 
   /* Next: overflow.  */
   if (FE_OVERFLOW & excepts)
-    /* I don't think we can do the same trick as intel so we will have
-       to live with inexact coming also.  */
-    fexceptadd (FLT_MAX, 1.0e32);
+    {
+#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
+      fexceptround (0x1p128);
+#else
+      /* If overflow-mask bit is zero, both IEEE-overflow and IEEE-inexact flags
+	 are set.  If overflow-mask bit is one, DXC field is set to 0x2C "IEEE
+	 overflow, inexact and incremented".  */
+      fexceptadd (FLT_MAX, 1.0e32);
+#endif
+    }
 
   /* Next: underflow.  */
   if (FE_UNDERFLOW & excepts)
-    fexceptdiv (FLT_MIN, 3.0);
+    {
+#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
+      fexceptround (0x1p-150);
+#else
+      /* If underflow-mask bit is zero, both IEEE-underflow and IEEE-inexact
+	 flags are set.  If underflow-mask bit is one, DXC field is set to 0x1C
+	 "IEEE underflow, inexact and incremented".  */
+      fexceptdiv (FLT_MIN, 3.0);
+#endif
+    }
 
   /* Last: inexact.  */
   if (FE_INEXACT & excepts)
diff --git a/sysdeps/s390/fpu/fsetexcptflg.c b/sysdeps/s390/fpu/fsetexcptflg.c
index 25ade854bd..56a52c6bb7 100644
--- a/sysdeps/s390/fpu/fsetexcptflg.c
+++ b/sysdeps/s390/fpu/fsetexcptflg.c
@@ -45,8 +45,7 @@ fesetexceptflag (const fexcept_t *flagp, int excepts)
     & newexcepts;
 
   /* Store the new status word (along with the rest of the environment.
-     Possibly new exceptions are set but they won't get executed unless
-     the next floating-point instruction.  */
+     Possibly new exceptions are set but they won't get executed.  */
   _FPU_SETCW (temp);
 
   /* Success.  */