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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-29 10:25:23 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-29 10:25:23 -0800 |
| commit | ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5 (patch) | |
| tree | 3ef42adf948b0e4f65e39e21f5c4a49da7e0b34f /sysdeps/riscv/start.S | |
| parent | 4215e27674de95a564087a3841873f3d980d4764 (diff) | |
| download | glibc-ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5.tar.gz glibc-ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5.tar.xz glibc-ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5.zip | |
Add documentation for __riscv_flush_icache
This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.
2018-01-29 Palmer Dabbelt <palmer@sifive.com>
* manual/platform.texi: Add RISC-V documenation for
__riscv_flush_icache.
Diffstat (limited to 'sysdeps/riscv/start.S')
0 files changed, 0 insertions, 0 deletions