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author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-12-26 20:51:24 -0800 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-29 10:25:29 -0800 |
commit | c776fa113da1f0d0cf83418e8937c0a8a4d83d3e (patch) | |
tree | 5aa9172a85e80592e4fb4f05c4bf53444612338f /sysdeps/riscv/dl-trampoline.S | |
parent | ba9e25a62bd662ce8c7ed6c8d1c072110f1ffae5 (diff) | |
download | glibc-c776fa113da1f0d0cf83418e8937c0a8a4d83d3e.tar.gz glibc-c776fa113da1f0d0cf83418e8937c0a8a4d83d3e.tar.xz glibc-c776fa113da1f0d0cf83418e8937c0a8a4d83d3e.zip |
RISC-V: ABI Implementation
This patch contains code that needs to directly know about the RISC-V ABI, which is specified in a work-in-progress psABI document: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md This is meant to contain all the RISC-V code that needs to explicitly name registers or manage in-memory structure layout. This does not contain any of the Linux-specific code. 2018-01-29 Palmer Dabbelt <palmer@sifive.com> * sysdeps/riscv/__longjmp.S: New file. * sysdeps/riscv/backtrace.c: Likewise. * sysdeps/riscv/bits/endian.h: Likewise. * sysdeps/riscv/bits/setjmp.h: Likewise. * sysdeps/riscv/bits/wordsize.h: Likewise. * sysdeps/riscv/bsd-_setjmp.c: Likewise. * sysdeps/riscv/bsd-setjmp.c: Likewise. * sysdeps/riscv/dl-trampoline.S: Likewise. * sysdeps/riscv/gccframe.h: Likewise. * sysdeps/riscv/jmpbuf-offsets.h: Likewise. * sysdeps/riscv/jmpbuf-unwind.h: Likewise. * sysdeps/riscv/machine-gmon.h: Likewise. * sysdeps/riscv/memusage.h: Likewise. * sysdeps/riscv/setjmp.S: Likewise. * sysdeps/riscv/sys/asm.h: Likewise. * sysdeps/riscv/tls-macros.h: Likewise.
Diffstat (limited to 'sysdeps/riscv/dl-trampoline.S')
-rw-r--r-- | sysdeps/riscv/dl-trampoline.S | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/sysdeps/riscv/dl-trampoline.S b/sysdeps/riscv/dl-trampoline.S new file mode 100644 index 0000000000..cda3be9f4e --- /dev/null +++ b/sysdeps/riscv/dl-trampoline.S @@ -0,0 +1,90 @@ +/* RISC-V PLT trampoline + Copyright (C) 2017-2018 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <sys/asm.h> + +/* Assembler veneer called from the PLT header code for lazy loading. + The PLT header passes its own args in t0-t2. */ + +#ifdef __riscv_float_abi_soft +# define FRAME_SIZE (-((-10 * SZREG) & ALMASK)) +#else +# define FRAME_SIZE (-((-10 * SZREG - 8 * SZFREG) & ALMASK)) +#endif + +ENTRY (_dl_runtime_resolve) + # Save arguments to stack. + addi sp, sp, -FRAME_SIZE + REG_S ra, 9*SZREG(sp) + REG_S a0, 1*SZREG(sp) + REG_S a1, 2*SZREG(sp) + REG_S a2, 3*SZREG(sp) + REG_S a3, 4*SZREG(sp) + REG_S a4, 5*SZREG(sp) + REG_S a5, 6*SZREG(sp) + REG_S a6, 7*SZREG(sp) + REG_S a7, 8*SZREG(sp) + +#ifndef __riscv_float_abi_soft + FREG_S fa0, (10*SZREG + 0*SZFREG)(sp) + FREG_S fa1, (10*SZREG + 1*SZFREG)(sp) + FREG_S fa2, (10*SZREG + 2*SZFREG)(sp) + FREG_S fa3, (10*SZREG + 3*SZFREG)(sp) + FREG_S fa4, (10*SZREG + 4*SZFREG)(sp) + FREG_S fa5, (10*SZREG + 5*SZFREG)(sp) + FREG_S fa6, (10*SZREG + 6*SZFREG)(sp) + FREG_S fa7, (10*SZREG + 7*SZFREG)(sp) +#endif + + # Update .got.plt and obtain runtime address of callee. + slli a1, t1, 1 + mv a0, t0 # link map + add a1, a1, t1 # reloc offset (== thrice the .got.plt offset) + la a2, _dl_fixup + jalr a2 + mv t1, a0 + + # Restore arguments from stack. + REG_L ra, 9*SZREG(sp) + REG_L a0, 1*SZREG(sp) + REG_L a1, 2*SZREG(sp) + REG_L a2, 3*SZREG(sp) + REG_L a3, 4*SZREG(sp) + REG_L a4, 5*SZREG(sp) + REG_L a5, 6*SZREG(sp) + REG_L a6, 7*SZREG(sp) + REG_L a7, 8*SZREG(sp) + +#ifndef __riscv_float_abi_soft + FREG_L fa0, (10*SZREG + 0*SZFREG)(sp) + FREG_L fa1, (10*SZREG + 1*SZFREG)(sp) + FREG_L fa2, (10*SZREG + 2*SZFREG)(sp) + FREG_L fa3, (10*SZREG + 3*SZFREG)(sp) + FREG_L fa4, (10*SZREG + 4*SZFREG)(sp) + FREG_L fa5, (10*SZREG + 5*SZFREG)(sp) + FREG_L fa6, (10*SZREG + 6*SZFREG)(sp) + FREG_L fa7, (10*SZREG + 7*SZFREG)(sp) +#endif + + addi sp, sp, FRAME_SIZE + + # Invoke the callee. + jr t1 +END (_dl_runtime_resolve) |