diff options
author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 14:04:45 -0500 |
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committer | Paul A. Clarke <pc@us.ibm.com> | 2019-11-13 15:37:19 -0600 |
commit | 54486d8bf8663143fa506bf2b6906f7cbbbd0db8 (patch) | |
tree | 2ffe3b762fce824c42eacd0945ff59e77db8387d /sysdeps/powerpc | |
parent | f8a5de73854ee1d90f2482327f5cf0778e54524b (diff) | |
download | glibc-54486d8bf8663143fa506bf2b6906f7cbbbd0db8.tar.gz glibc-54486d8bf8663143fa506bf2b6906f7cbbbd0db8.tar.xz glibc-54486d8bf8663143fa506bf2b6906f7cbbbd0db8.zip |
[powerpc] Rename fesetenv_mode to fesetenv_control
fesetenv_mode is used variously to write the FPSCR exception enable bits and rounding mode bits. These are referred to as the control bits in the POWER ISA. Change the name to be reflective of its current and expected use, and match up well with fegetenv_control.
Diffstat (limited to 'sysdeps/powerpc')
-rw-r--r-- | sysdeps/powerpc/fpu/fedisblxcpt.c | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/feenablxcpt.c | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fenv_private.h | 4 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fesetmode.c | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 65fe4313f5..70dbc65a7e 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -41,7 +41,7 @@ fedisableexcept (int excepts) fe.l &= ~new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index d025a44e24..8be82a0f58 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -41,7 +41,7 @@ feenableexcept (int excepts) fe.l |= new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_EXIT_NON_STOP (0ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 0dc81fc2d3..df38487a55 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -116,7 +116,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Set the last 2 nibbles of the FPSCR, which contain the exception enables and the rounding mode. 'fegetenv_control' retrieves these bits by reading the FPSCR. */ -#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env)); +#define fesetenv_control(env) __builtin_mtfsf (0b00000011, (env)); /* This very handy macro: - Sets the rounding mode to 'round to nearest'; diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index 084289ec50..452d531b71 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -61,7 +61,7 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) && (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK)) { - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); } else /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ @@ -142,7 +142,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) if (__glibc_unlikely (new.l != old.l)) { __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); ctx->updated_status = true; } else diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index bda2218210..72acdaf5eb 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -36,6 +36,6 @@ fesetmode (const femode_t *modep) __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); return 0; } |