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authorUlrich Drepper <drepper@redhat.com>2009-01-30 20:30:46 +0000
committerUlrich Drepper <drepper@redhat.com>2009-01-30 20:30:46 +0000
commitb7219e53bcd54d874f85c67469f4c1dd4f2ad5d2 (patch)
treeb8fa9a8c297254d44f7cd3a68b0370557e42dfd6 /sysdeps/powerpc
parenta3bd28468c9f309d3f89815476e6ae16c7342d92 (diff)
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[BZ #9726]
2009-01-11  Ryan S. Arnold  <rsa@us.ibm.com>
	[BZ #9726]
	* sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_SET_DI_FPSCR,
	_SET_SI_FPSCR): Clobber fp0 to prevent erroneous test-case passes.

2009-01-08  Ryan S. Arnold  <rsa@us.ibm.com>

	[BZ #9726]
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
	(__CONTEXT_FUNC_NAME): Fix mtfsf to use fp31 instead of fp0.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
	(__CONTEXT_FUNC_NAME): Fix mtfsf to use fp31 instead of fp0.
Diffstat (limited to 'sysdeps/powerpc')
-rw-r--r--sysdeps/powerpc/fpu/tst-setcontext-fpscr.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
index 973fb3f77a..a15fe86fb9 100644
--- a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
+++ b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
@@ -1,4 +1,4 @@
-/* Copyright (C) 2001,2002,2004,2006,2007,2008 Free Software Foundation, Inc.
+/* Copyright (C) 2001,2002,2004,2006-2008,2009 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Ryan S. Arnold <rsa@us.ibm.com>
                   Sean Curry <spcurry@us.ibm.com>
@@ -104,12 +104,16 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
    (__fpscr)=tmp.fpscr;							     \
    tmp.fpscr; })
 
+/* We make sure to zero fp0 after we use it in order to prevent stale data
+   in an fp register from making a test-case pass erroneously.  */
 # define _SET_DI_FPSCR(__fpscr) {					     \
   union { double d; di_fpscr_t fpscr; }					     \
     tmp __attribute__ ((__aligned__(8)));				     \
   tmp.fpscr = __fpscr;							     \
   /* Set the entire 64-bit FPSCR.  */					     \
   __asm__ ("lfd%U0 0,%0; mtfsf 255,0,1,0" : : "m" (tmp.d) : "fr0");	     \
+  tmp.d = 0;								     \
+  __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0");			     \
 }
 
 # define _GET_SI_FPSCR(__fpscr) ({					     \
@@ -120,6 +124,8 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
    (__fpscr)=tmp.cw[1];							     \
    tmp.cw[0]; })
 
+/* We make sure to zero fp0 after we use it in order to prevent stale data
+   in an fp register from making a test-case pass erroneously.  */
 # define _SET_SI_FPSCR(__fpscr) {					     \
   union { double d; si_fpscr_t fpscr[2]; }				     \
     tmp __attribute__ ((__aligned__(8)));				     \
@@ -127,6 +133,8 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
   tmp.fpscr[0] = 0xFFF80000;						     \
   tmp.fpscr[1] = __fpscr;						     \
   __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0");		     \
+  tmp.d = 0;								     \
+  __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0");			     \
 }
 
 void prime_special_regs(int which)