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authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>2013-05-24 13:29:30 -0500
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>2013-05-24 13:29:30 -0500
commitd116b7c414c8239b677e341ac517745db689ac2d (patch)
treea019a5bc401ad70db2b5991555488ce85193fb03 /sysdeps/powerpc
parente96e37676f0b3dd2a7c42898bbf9aabb90f91d75 (diff)
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PowerPC: Program Priority Register support
This patch add inline functions to change the Program Priority Register
from ISA 2.05.
Diffstat (limited to 'sysdeps/powerpc')
-rw-r--r--sysdeps/powerpc/sys/platform/ppc.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/sysdeps/powerpc/sys/platform/ppc.h b/sysdeps/powerpc/sys/platform/ppc.h
index 833f3d8480..81f3bf9bff 100644
--- a/sysdeps/powerpc/sys/platform/ppc.h
+++ b/sysdeps/powerpc/sys/platform/ppc.h
@@ -82,4 +82,34 @@ __ppc_mdoom (void)
   __asm__ volatile ("or 30,30,30");
 }
 
+
+/* ISA 2.05 and beyond support the Program Priority Register (PPR) to adjust
+   thread priorities based on lock acquisition, wait and release. The ISA
+   defines the use of form 'or Rx,Rx,Rx' as the way to modify the PRI field.
+   The unprivileged priorities are:
+     Rx = 1 (low)
+     Rx = 2 (medium)
+     Rx = 6 (medium-low/normal)
+   The 'or' instruction form is a nop in previous hardware, so it is safe to
+   use unguarded. The default value is 'medium'.
+ */
+
+static inline void
+__ppc_set_ppr_med (void)
+{
+  __asm__ volatile ("or 2,2,2");
+}
+
+static inline void
+__ppc_set_ppr_med_low (void)
+{
+  __asm__ volatile ("or 6,6,6");
+}
+
+static inline void
+__ppc_set_ppr_low (void)
+{
+  __asm__ volatile ("or 1,1,1");
+}
+
 #endif  /* sys/platform/ppc.h */