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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-03-31 08:00:38 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-03-31 08:00:38 -0500 |
| commit | 757d9dd5c3efa56fac75965abc014faaae7b7895 (patch) | |
| tree | ce9ba1eeb3c3bb42716f669d9117ac5068e1663b /sysdeps/powerpc/powerpc64 | |
| parent | 47c5adebd2c864a098c3af66e61e1147dc3cf0b4 (diff) | |
| download | glibc-757d9dd5c3efa56fac75965abc014faaae7b7895.tar.gz glibc-757d9dd5c3efa56fac75965abc014faaae7b7895.tar.xz glibc-757d9dd5c3efa56fac75965abc014faaae7b7895.zip | |
PowerPC: Fix little endian enconding for mfvsrd
This patch fixes the MFVSRD_R3_V1 macro that encodes 'mfvsrd r3,vs1' (to support old binutils) for little endian.
Diffstat (limited to 'sysdeps/powerpc/powerpc64')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S | 5 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S | 5 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S | 5 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S | 5 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S | 5 |
5 files changed, 25 insertions, 0 deletions
diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S index 8e5de271c6..2b27e7b923 100644 --- a/sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S @@ -17,9 +17,14 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <endian.h> #include <math_ldbl_opt.h> +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */ +#else #define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ +#endif /* int [r3] __finite ([fp1] x) */ diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S index 0e92af8d9f..d09b7fcef9 100644 --- a/sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S @@ -17,9 +17,14 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <endian.h> #include <math_ldbl_opt.h> +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */ +#else #define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ +#endif /* int [r3] __isinf([fp1] x) */ diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S index c1ca9a5b89..b03c896acf 100644 --- a/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S @@ -17,9 +17,14 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <endian.h> #include <math_ldbl_opt.h> +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */ +#else #define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ +#endif /* int [r3] __isnan([f1] x) */ diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S index 476d76bf7b..9a55d93875 100644 --- a/sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S @@ -17,9 +17,14 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <endian.h> #include <math_ldbl_opt.h> +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */ +#else #define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ +#endif /* long long int[r3] __llrint (double x[fp1]) */ ENTRY (__llrint) diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S index b00d4d616f..f10c06a36c 100644 --- a/sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S @@ -17,9 +17,14 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <endian.h> #include <math_ldbl_opt.h> +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */ +#else #define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ +#endif /* long long [r3] llround (float x [fp1]) */ |