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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 09:45:41 -0600 |
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| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:33 -0600 |
| commit | 4393fc119c34e97519b9b7a4fc94066b283be452 (patch) | |
| tree | dffac0629930499b0f88886fca4f1b094ef74fa5 /sysdeps/powerpc/powerpc64/fpu/s_lrint.S | |
| parent | 487972aea52004f604c2878c8c9d3e77670f2c32 (diff) | |
| download | glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.gz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.xz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.zip | |
PowerPC: Optimized isinf/isinff for POWER8
This patch add a optimized isinf/isinff implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/fpu/s_lrint.S')
0 files changed, 0 insertions, 0 deletions