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authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>2014-02-27 09:43:51 -0600
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>2014-02-27 12:58:32 -0600
commit487972aea52004f604c2878c8c9d3e77670f2c32 (patch)
tree1f8a570e52975d04c513523e7d7b454a29015993 /sysdeps/powerpc/powerpc32
parent7d92b78723848ae616709eb8f0191ea067025b18 (diff)
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PowerPC: Optimized isnan/isnanf for POWER8
This patch add a optimized isnan/isnanf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc32')
-rw-r--r--sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h b/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
index 51a34f2588..72d720d55a 100644
--- a/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
+++ b/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
@@ -36,6 +36,7 @@
    and fills the previous ones.  */
 #define INIT_ARCH() \
   unsigned long int hwcap = __GLRO(dl_hwcap); 			\
+  unsigned long int __attribute__((unused)) hwcap2 = __GLRO(dl_hwcap2); \
   if (hwcap & PPC_FEATURE_ARCH_2_06)				\
     hwcap |= PPC_FEATURE_ARCH_2_05 |				\
 	     PPC_FEATURE_POWER5_PLUS |				\