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| author | Ulrich Drepper <drepper@redhat.com> | 2007-07-12 18:38:01 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2007-07-12 18:38:01 +0000 |
| commit | a88f47a72f4ca65832584a3f5a591690f6675092 (patch) | |
| tree | 6876a751bd4c5c3fab26e1a323a4f63a166e01cc /sysdeps/powerpc/powerpc32/power4 | |
| parent | 1c298d08873e72a2339161517da660bdaff0e3f8 (diff) | |
| download | glibc-a88f47a72f4ca65832584a3f5a591690f6675092.tar.gz glibc-a88f47a72f4ca65832584a3f5a591690f6675092.tar.xz glibc-a88f47a72f4ca65832584a3f5a591690f6675092.zip | |
* sysdeps/powerpc/powerpc32/power6/memset.S: Update comments.
Specify .machine power6 to get ISA-V2.0 branch hints. Unroll loops and avoid branch misspredicts for > 31 bytes memset case. * sysdeps/powerpc/powerpc64/power6/memset.S: Likewise. Remove toc ref to __cache_line_size. * sysdeps/powerpc/powerpc32/power4/memcmp.S: Specify .machine power4 to get ISA-V2.0 branch hints. * sysdeps/powerpc/powerpc32/power4/memcpy.S: Likewise * sysdeps/powerpc/powerpc32/power4/memset.S: Likewise * sysdeps/powerpc/powerpc32/power6/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memset.S: Likewise. Remove toc ref to __cache_line_size. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Include math_ldbl_opt.h.
Diffstat (limited to 'sysdeps/powerpc/powerpc32/power4')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/power4/memcmp.S | 1 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc32/power4/memcpy.S | 1 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc32/power4/memset.S | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/powerpc/powerpc32/power4/memcmp.S b/sysdeps/powerpc/powerpc32/power4/memcmp.S index 4715302739..75b328403a 100644 --- a/sysdeps/powerpc/powerpc32/power4/memcmp.S +++ b/sysdeps/powerpc/powerpc32/power4/memcmp.S @@ -23,6 +23,7 @@ /* int [r3] memcmp (const char *s1 [r3], const char *s2 [r4], size_t size [r5]) */ + .machine power4 EALIGN (BP_SYM(memcmp), 4, 0) CALL_MCOUNT diff --git a/sysdeps/powerpc/powerpc32/power4/memcpy.S b/sysdeps/powerpc/powerpc32/power4/memcpy.S index c48db2f3df..73020c6da8 100644 --- a/sysdeps/powerpc/powerpc32/power4/memcpy.S +++ b/sysdeps/powerpc/powerpc32/power4/memcpy.S @@ -34,6 +34,7 @@ possible when both source and destination are word aligned. Each case has an optimized unrolled loop. */ + .machine power4 EALIGN (BP_SYM (memcpy), 5, 0) CALL_MCOUNT diff --git a/sysdeps/powerpc/powerpc32/power4/memset.S b/sysdeps/powerpc/powerpc32/power4/memset.S index b07ed3c2d3..5dd1d943cf 100644 --- a/sysdeps/powerpc/powerpc32/power4/memset.S +++ b/sysdeps/powerpc/powerpc32/power4/memset.S @@ -28,6 +28,7 @@ cache line (1024 bits). There is a special case for setting cache lines to 0, to take advantage of the dcbz instruction. */ + .machine power4 EALIGN (BP_SYM (memset), 5, 0) CALL_MCOUNT |