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| author | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
| commit | 9c84384cc18ff589233628c193953ca8d7a39f5c (patch) | |
| tree | 95d1f5aee409b208db7545d678012eeae9559fae /sysdeps/powerpc/powerpc32/power4/memset.S | |
| parent | 5556231db2301917cd14a7450de4eba2368c9763 (diff) | |
| download | glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.gz glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.xz glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.zip | |
Remove trailing whitespace.
Diffstat (limited to 'sysdeps/powerpc/powerpc32/power4/memset.S')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/power4/memset.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/powerpc/powerpc32/power4/memset.S b/sysdeps/powerpc/powerpc32/power4/memset.S index 1e8785cb4a..c2d288b38b 100644 --- a/sysdeps/powerpc/powerpc32/power4/memset.S +++ b/sysdeps/powerpc/powerpc32/power4/memset.S @@ -162,7 +162,7 @@ L(cacheAligned): add rMEMP,rMEMP,rCLS b L(cacheAligned) -/* We are here because the cache line size was set and the remainder +/* We are here because the cache line size was set and the remainder (rLEN) is less than the actual cache line size. So set up the preconditions for L(nondcbz) and go there. */ L(handletail32): |