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author | Alan Modra <amodra@gmail.com> | 2013-08-17 18:31:45 +0930 |
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committer | Alan Modra <amodra@gmail.com> | 2013-10-04 10:35:43 +0930 |
commit | 7b88401f3b25325b1381798a0eccb3efe7751fec (patch) | |
tree | 862973bae84d0411a612406f7801529f1e3caf45 /sysdeps/powerpc/powerpc32/fpu | |
parent | 9c008155b7d5d1bd81d909497850a2ece28aec50 (diff) | |
download | glibc-7b88401f3b25325b1381798a0eccb3efe7751fec.tar.gz glibc-7b88401f3b25325b1381798a0eccb3efe7751fec.tar.xz glibc-7b88401f3b25325b1381798a0eccb3efe7751fec.zip |
PowerPC floating point little-endian [12 of 15]
http://sourceware.org/ml/libc-alpha/2013-08/msg00087.html Fixes for little-endian in 32-bit assembly. * sysdeps/powerpc/sysdep.h (LOWORD, HIWORD, HISHORT): Define. * sysdeps/powerpc/powerpc32/fpu/s_copysign.S: Load little-endian words of double from correct stack offsets. * sysdeps/powerpc/powerpc32/fpu/s_copysignl.S: Likewise. * sysdeps/powerpc/powerpc32/fpu/s_lrint.S: Likewise. * sysdeps/powerpc/powerpc32/fpu/s_lround.S: Likewise. * sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S: Likewise. * sysdeps/powerpc/powerpc32/power5/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Use HISHORT. * sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise.
Diffstat (limited to 'sysdeps/powerpc/powerpc32/fpu')
-rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_copysign.S | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_copysignl.S | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_lrint.S | 4 | ||||
-rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_lround.S | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/sysdeps/powerpc/powerpc32/fpu/s_copysign.S b/sysdeps/powerpc/powerpc32/fpu/s_copysign.S index 840891f1c3..1da24f492e 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_copysign.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_copysign.S @@ -29,7 +29,7 @@ ENTRY(__copysign) stwu r1,-16(r1) cfi_adjust_cfa_offset (16) stfd fp2,8(r1) - lwz r3,8(r1) + lwz r3,8+HIWORD(r1) cmpwi r3,0 addi r1,r1,16 cfi_adjust_cfa_offset (-16) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S index 4ec8389b5d..2ad6de273d 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S @@ -30,7 +30,7 @@ ENTRY(__copysignl) fmr fp0,fp1 fabs fp1,fp1 fcmpu cr7,fp0,fp1 - lwz r3,8(r1) + lwz r3,8+HIWORD(r1) cmpwi cr6,r3,0 addi r1,r1,16 cfi_adjust_cfa_offset (-16) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_lrint.S b/sysdeps/powerpc/powerpc32/fpu/s_lrint.S index 27881f8cc7..249fda501f 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_lrint.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_lrint.S @@ -24,10 +24,10 @@ ENTRY (__lrint) stwu r1,-16(r1) fctiw fp13,fp1 stfd fp13,8(r1) - nop /* Insure the following load is in a different dispatch group */ + nop /* Ensure the following load is in a different dispatch group */ nop /* to avoid pipe stall on POWER4&5. */ nop - lwz r3,12(r1) + lwz r3,8+LOWORD(r1) addi r1,r1,16 blr END (__lrint) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_lround.S b/sysdeps/powerpc/powerpc32/fpu/s_lround.S index 92dc3787d6..6309f864b7 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_lround.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_lround.S @@ -67,7 +67,7 @@ ENTRY (__lround) nop /* Ensure the following load is in a different dispatch */ nop /* group to avoid pipe stall on POWER4&5. */ nop - lwz r3,12(r1) /* Load return as integer. */ + lwz r3,8+LOWORD(r1) /* Load return as integer. */ .Lout: addi r1,r1,16 blr |