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| author | Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> | 2020-01-10 19:14:56 -0300 |
|---|---|---|
| committer | Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> | 2020-01-17 09:05:03 -0300 |
| commit | 18363b4f010da9ba459b13310b113ac0647c2fcc (patch) | |
| tree | a9b4b22d7fb65d7d219eb0e10b996de971da54e9 /sysdeps/powerpc/powerpc32/a2/memcpy.S | |
| parent | c908ae0492cb9c68736306e2bceec7244a940568 (diff) | |
| download | glibc-18363b4f010da9ba459b13310b113ac0647c2fcc.tar.gz glibc-18363b4f010da9ba459b13310b113ac0647c2fcc.tar.xz glibc-18363b4f010da9ba459b13310b113ac0647c2fcc.zip | |
powerpc: Move cache line size to rtld_global_ro
GCC 10.0 enabled -fno-common by default and this started to point that __cache_line_size had been implemented in 2 different places: loader and libc. In order to avoid this duplication, the libc variable has been removed and the loader variable is moved to rtld_global_ro. File sysdeps/unix/sysv/linux/powerpc/dl-auxv.h has been added in order to reuse code for both static and dynamic linking scenarios. Reviewed-by: Carlos O'Donell <carlos@redhat.com>
Diffstat (limited to 'sysdeps/powerpc/powerpc32/a2/memcpy.S')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/a2/memcpy.S | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/sysdeps/powerpc/powerpc32/a2/memcpy.S b/sysdeps/powerpc/powerpc32/a2/memcpy.S index fe5dab847a..6f4d8a7b34 100644 --- a/sysdeps/powerpc/powerpc32/a2/memcpy.S +++ b/sysdeps/powerpc/powerpc32/a2/memcpy.S @@ -18,6 +18,7 @@ <https://www.gnu.org/licenses/>. */ #include <sysdep.h> +#include <rtld-global-offsets.h> #define PREFETCH_AHEAD 4 /* no cache lines SRC prefetching ahead */ #define ZERO_AHEAD 2 /* no cache lines DST zeroing ahead */ @@ -106,25 +107,23 @@ EALIGN (memcpy, 5, 0) L(dst_aligned): -#ifdef SHARED +#ifdef PIC mflr r0 -/* Establishes GOT addressability so we can load __cache_line_size - from static. This value was set from the aux vector during startup. */ +/* Establishes GOT addressability so we can load the cache line size + from rtld_global_ro. This value was set from the aux vector during + startup. */ SETUP_GOT_ACCESS(r9,got_label) - addis r9,r9,__cache_line_size-got_label@ha - lwz r9,__cache_line_size-got_label@l(r9) - mtlr r0 -#else -/* Load __cache_line_size from static. This value was set from the - aux vector during startup. */ - lis r9,__cache_line_size@ha - lwz r9,__cache_line_size@l(r9) + addis r9,r9,_GLOBAL_OFFSET_TABLE_-got_label@ha + addi r9,r9,_GLOBAL_OFFSET_TABLE_-got_label@l + mtlr r0 #endif + __GLRO(r9, r9, _dl_cache_line_size, + RTLD_GLOBAL_RO_DL_CACHE_LINE_SIZE_OFFSET) cmplwi cr5, r9, 0 bne+ cr5,L(cachelineset) -/* __cache_line_size not set: generic byte copy without much optimization */ +/* Cache line size not set: generic byte copy without much optimization */ andi. r0,r5,1 /* If length is odd copy one byte. */ beq L(cachelinenotset_align) lbz r7,0(r4) /* Read one byte from source. */ |