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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 11:39:44 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 08:53:01 -0500 |
| commit | e68b1151f7460d5fa88c3a567c13f66052da79a7 (patch) | |
| tree | 5ad422da01176650d27386a6901ca53c5630b2b8 /sysdeps/powerpc/fpu | |
| parent | 7413c188c77adb26a15cf0e98e0a991d09d73c65 (diff) | |
| download | glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.tar.gz glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.tar.xz glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.zip | |
[powerpc] __fesetround_inline optimizations
On POWER9, use more efficient means to update the 2-bit rounding mode via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions or one 'mtfsfi' instruction that modifies 4 bits). Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com> Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
Diffstat (limited to 'sysdeps/powerpc/fpu')
| -rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index d5e458756a..06bd9bad4c 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -148,7 +148,12 @@ typedef union static inline int __fesetround_inline (int round) { - if ((unsigned int) round < 2) +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else if ((unsigned int) round < 2) { asm volatile ("mtfsb0 30"); if ((unsigned int) round == 0) @@ -164,7 +169,7 @@ __fesetround_inline (int round) else asm volatile ("mtfsb1 31"); } - +#endif return 0; } @@ -173,7 +178,14 @@ __fesetround_inline (int round) static inline void __fesetround_inline_nocheck (const int round) { - asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else + asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#endif } #define FPSCR_MASK(bit) (1 << (31 - (bit))) |