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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2015-01-27 06:37:10 -0600 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2015-01-28 05:59:21 -0500 |
| commit | d4d0ecb24474928b9dfcce6c3f09694fab2400b6 (patch) | |
| tree | fb1446f69193dbf2b07a1bc52c42dac10dafd3a8 /sysdeps/powerpc/fpu | |
| parent | 08cee2a464f614a6d4275b5af6c52481f1aa16e6 (diff) | |
| download | glibc-d4d0ecb24474928b9dfcce6c3f09694fab2400b6.tar.gz glibc-d4d0ecb24474928b9dfcce6c3f09694fab2400b6.tar.xz glibc-d4d0ecb24474928b9dfcce6c3f09694fab2400b6.zip | |
powerpc: Fix fesetexceptflag [BZ#17885]
This patch fixes a bug introduced by 18f2945ae9216cfc, where it optimizes the FPSCR set by just issuing a mtfs instruction if new flag is different from older one. The issue is a typo, where the new flag should the the new value, instead of the old one. It fixes BZ#17885.
Diffstat (limited to 'sysdeps/powerpc/fpu')
| -rw-r--r-- | sysdeps/powerpc/fpu/fsetexcptflg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 5d99bf29b0..836d839285 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -40,7 +40,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (u.fenv); + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) |