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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 14:04:45 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 11:03:25 -0500 |
| commit | d7a568af5546e0313abbc04060c8e9b0d3f750b4 (patch) | |
| tree | 80878e5e076ca9ae78089ee80b321c1d057e3f80 /sysdeps/powerpc/fpu/s_logb.c | |
| parent | 36c17c7079a5243a890ba43affff326a041775a9 (diff) | |
| download | glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.gz glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.xz glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.zip | |
[powerpc] Rename fesetenv_mode to fesetenv_control
fesetenv_mode is used variously to write the FPSCR exception enable bits and rounding mode bits. These are referred to as the control bits in the POWER ISA. Change the name to be reflective of its current and expected use, and match up well with fegetenv_control.
Diffstat (limited to 'sysdeps/powerpc/fpu/s_logb.c')
0 files changed, 0 insertions, 0 deletions