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author | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
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committer | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
commit | 9c84384cc18ff589233628c193953ca8d7a39f5c (patch) | |
tree | 95d1f5aee409b208db7545d678012eeae9559fae /sysdeps/powerpc/fpu/feupdateenv.c | |
parent | 5556231db2301917cd14a7450de4eba2368c9763 (diff) | |
download | glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.gz glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.xz glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.zip |
Remove trailing whitespace.
Diffstat (limited to 'sysdeps/powerpc/fpu/feupdateenv.c')
-rw-r--r-- | sysdeps/powerpc/fpu/feupdateenv.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c index 9faf930f36..6500ea1737 100644 --- a/sysdeps/powerpc/fpu/feupdateenv.c +++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -35,17 +35,17 @@ __feupdateenv (const fenv_t *envp) exceptions. Leave fraction rounded/inexact and FP result/CC bits unchanged. */ new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF); - + /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); - + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not + FPU to run faster because it always takes the default action and can not generate SIGFPE. */ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); |