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authorPaul A. Clarke <pc@us.ibm.com>2019-07-12 20:13:58 -0500
committerPaul A. Clarke <pc@us.ibm.com>2019-08-28 13:49:19 -0500
commitcd7ce12a027656ad3cda774454088de5a2c7fbfa (patch)
treeae1686c96b9c3e627df3123eaa6f329db5a5b174 /sysdeps/powerpc/fpu/fesetmode.c
parent35ffd20dbd76d3cb6b478c7a69bb40d8c827ed81 (diff)
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[powerpc] fe{en,dis}ableexcept optimize bit translations
The exceptions passed to fe{en,dis}ableexcept() are defined in the ABI
as a bitmask, a combination of FE_INVALID, FE_OVERFLOW, etc.
Within the functions, these bits must be translated to/from the corresponding
enable bits in the Floating Point Status Control Register (FPSCR).
This translation is currently done bit-by-bit.  The compiler generates
a series of conditional bit operations.  Nicely, the "FE" exception
bits are all a uniform offset from the FPSCR enable bits, so the bit-by-bit
operation can instead be performed by a shift with appropriate masking.
Diffstat (limited to 'sysdeps/powerpc/fpu/fesetmode.c')
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