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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-28 14:38:24 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-29 07:05:39 -0500 |
| commit | 18f2945ae9216cfcd53a162080a73e3d719de9e6 (patch) | |
| tree | 8d529fe01c41f0d3c6dd290aa69dbf4e5d6e083f /sysdeps/powerpc/fpu/fesetenv.c | |
| parent | 5abebba403181de898bbea4ee1bcce5f088c663b (diff) | |
| download | glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.gz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.xz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.zip | |
PowerPC: Suppress unnecessary FPSCR write
This patch optimizes the FPSCR update on exception and rounding change functions by just updating its value if new value if different from current one. It also optimizes fedisableexcept and feenableexcept by removing an unecessary FPSCR read.
Diffstat (limited to 'sysdeps/powerpc/fpu/fesetenv.c')
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index fa99ddbd40..138bde0685 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -29,6 +29,8 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; old.fenv = fegetenv_register (); + if (old.l == new.l) + return 0; /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the |