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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 11:58:46 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 08:53:50 -0500 |
| commit | 81ecb0ee4970865cbe5d1da733c4879b999c528f (patch) | |
| tree | 7e74bf5638280f636a9231f0dcc9e0b427961c77 /sysdeps/powerpc/fpu/fenv_const.c | |
| parent | e68b1151f7460d5fa88c3a567c13f66052da79a7 (diff) | |
| download | glibc-81ecb0ee4970865cbe5d1da733c4879b999c528f.tar.gz glibc-81ecb0ee4970865cbe5d1da733c4879b999c528f.tar.xz glibc-81ecb0ee4970865cbe5d1da733c4879b999c528f.zip | |
[powerpc] Rename fegetenv_status to fegetenv_control
fegetenv_status is used variously to retrieve the FPSCR exception enable bits, rounding mode bits, or both. These are referred to as the control bits in the POWER ISA. FPSCR status bits are also returned by the 'mffs' and 'mffsl' instructions, but they are uniformly ignored by all uses of fegetenv_status. Change the name to be reflective of its current and expected use. Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
Diffstat (limited to 'sysdeps/powerpc/fpu/fenv_const.c')
0 files changed, 0 insertions, 0 deletions