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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 11:31:31 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 11:01:54 -0500 |
| commit | 36c17c7079a5243a890ba43affff326a041775a9 (patch) | |
| tree | cba6527c4987bf4fef2c179b1b57beacaf8d73fc /sysdeps/powerpc/fpu/fenv_const.c | |
| parent | 81ecb0ee4970865cbe5d1da733c4879b999c528f (diff) | |
| download | glibc-36c17c7079a5243a890ba43affff326a041775a9.tar.gz glibc-36c17c7079a5243a890ba43affff326a041775a9.tar.xz glibc-36c17c7079a5243a890ba43affff326a041775a9.zip | |
[powerpc] libc_feholdsetround_noex_ppc_ctx: optimize FPSCR write
libc_feholdsetround_noex_ppc_ctx currently performs: 1. Read FPSCR, save to context. 2. Create new FPSCR value: clear enables and set new rounding mode. 3. Write new value to FPSCR. Since other bits just pass through, there is no need to write them. Instead, write just the changed values (enables and rounding mode), which can be a bit more efficient.
Diffstat (limited to 'sysdeps/powerpc/fpu/fenv_const.c')
0 files changed, 0 insertions, 0 deletions