summary refs log tree commit diff
path: root/sysdeps/powerpc/fpu/fedisblxcpt.c
diff options
context:
space:
mode:
authorPaul A. Clarke <pc@us.ibm.com>2019-09-19 14:04:45 -0500
committerPaul A. Clarke <pc@us.ibm.com>2019-09-27 11:03:25 -0500
commitd7a568af5546e0313abbc04060c8e9b0d3f750b4 (patch)
tree80878e5e076ca9ae78089ee80b321c1d057e3f80 /sysdeps/powerpc/fpu/fedisblxcpt.c
parent36c17c7079a5243a890ba43affff326a041775a9 (diff)
downloadglibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.gz
glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.xz
glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.zip
[powerpc] Rename fesetenv_mode to fesetenv_control
fesetenv_mode is used variously to write the FPSCR exception enable
bits and rounding mode bits.  These are referred to as the control
bits in the POWER ISA.  Change the name to be reflective of its
current and expected use, and match up well with fegetenv_control.
Diffstat (limited to 'sysdeps/powerpc/fpu/fedisblxcpt.c')
-rw-r--r--sysdeps/powerpc/fpu/fedisblxcpt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
index 870cfc8dbc..9f86c5fbef 100644
--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
@@ -41,7 +41,7 @@ fedisableexcept (int excepts)
   fe.l &= ~new;
 
   if (fe.l != curr.l)
-    fesetenv_mode (fe.fenv);
+    fesetenv_control (fe.fenv);
 
   __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l);