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| author | Ulrich Drepper <drepper@redhat.com> | 1998-09-09 22:40:55 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 1998-09-09 22:40:55 +0000 |
| commit | adac8450947aa7963df1ff143fa64e6579a0f620 (patch) | |
| tree | c6cc922ff494f53c3a265b027ded51417716c36d /sysdeps/powerpc/bits | |
| parent | 8e140239aeb0a5912ca04a164b25d31c3bbb4fc6 (diff) | |
| download | glibc-adac8450947aa7963df1ff143fa64e6579a0f620.tar.gz glibc-adac8450947aa7963df1ff143fa64e6579a0f620.tar.xz glibc-adac8450947aa7963df1ff143fa64e6579a0f620.zip | |
Update.
1998-09-09 Benjamin Kosnik <bkoz@tintin.cygnus.com> * math/libm-test.c (exp10_test): Adapt epsilons for powerpc. (csqrt_test): Likewise. * sysdeps/powerpc/bits/fenv.h: Add parens. .
Diffstat (limited to 'sysdeps/powerpc/bits')
| -rw-r--r-- | sysdeps/powerpc/bits/fenv.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/sysdeps/powerpc/bits/fenv.h b/sysdeps/powerpc/bits/fenv.h index 4f394fd64f..f86d02d014 100644 --- a/sysdeps/powerpc/bits/fenv.h +++ b/sysdeps/powerpc/bits/fenv.h @@ -25,13 +25,13 @@ the appropriate bits in the FPSCR... */ enum { - FE_INEXACT = 1 << 31-6, + FE_INEXACT = 1 << (31 - 6), #define FE_INEXACT FE_INEXACT - FE_DIVBYZERO = 1 << 31-5, + FE_DIVBYZERO = 1 << (31 - 5), #define FE_DIVBYZERO FE_DIVBYZERO - FE_UNDERFLOW = 1 << 31-4, + FE_UNDERFLOW = 1 << (31 - 4), #define FE_UNDERFLOW FE_UNDERFLOW - FE_OVERFLOW = 1 << 31-3, + FE_OVERFLOW = 1 << (31 - 3), #define FE_OVERFLOW FE_OVERFLOW /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID @@ -40,7 +40,7 @@ enum says that it must be a power of 2. Instead we use bit 2 which is the summary bit for all the FE_INVALID exceptions, which kind of makes sense. */ - FE_INVALID = 1 << 31-2, + FE_INVALID = 1 << (31 - 2), #define FE_INVALID FE_INVALID #ifdef __USE_GNU @@ -51,42 +51,42 @@ enum enable these exceptions individually. */ /* Operation with SNaN. */ - FE_INVALID_SNAN = 1 << 31-7, + FE_INVALID_SNAN = 1 << (31 - 7), # define FE_INVALID_SNAN FE_INVALID_SNAN /* Inf - Inf */ - FE_INVALID_ISI = 1 << 31-8, + FE_INVALID_ISI = 1 << (31 - 8), # define FE_INVALID_ISI FE_INVALID_ISI /* Inf / Inf */ - FE_INVALID_IDI = 1 << 31-9, + FE_INVALID_IDI = 1 << (31 - 9), # define FE_INVALID_IDI FE_INVALID_IDI /* 0 / 0 */ - FE_INVALID_ZDZ = 1 << 31-10, + FE_INVALID_ZDZ = 1 << (31 - 10), # define FE_INVALID_ZDZ FE_INVALID_ZDZ /* Inf * 0 */ - FE_INVALID_IMZ = 1 << 31-11, + FE_INVALID_IMZ = 1 << (31 - 11), # define FE_INVALID_IMZ FE_INVALID_IMZ /* Comparison with NaN or SNaN. */ - FE_INVALID_COMPARE = 1 << 31-12, + FE_INVALID_COMPARE = 1 << (31 - 12), # define FE_INVALID_COMPARE FE_INVALID_COMPARE /* Invalid operation flag for software (not set by hardware). */ /* Note that some chips don't have this implemented, presumably because no-one expected anyone to write software for them %-). */ - FE_INVALID_SOFTWARE = 1 << 31-21, + FE_INVALID_SOFTWARE = 1 << (31 - 21), # define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE /* Square root of negative number (including -Inf). */ /* Note that some chips don't have this implemented. */ - FE_INVALID_SQRT = 1 << 31-22, + FE_INVALID_SQRT = 1 << (31 - 22), # define FE_INVALID_SQRT FE_INVALID_SQRT /* Conversion-to-integer of a NaN or a number too large or too small. */ - FE_INVALID_INTEGER_CONVERSION = 1 << 31-23, + FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23), # define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION # define FE_ALL_INVALID \ |