diff options
| author | Ulrich Drepper <drepper@redhat.com> | 2007-05-07 06:22:38 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2007-05-07 06:22:38 +0000 |
| commit | 4a59e9adcb9e8475a00ea9088b26b74b48998dd0 (patch) | |
| tree | bd8ca665d3df88463cb4e328510db9625f9df75c /sysdeps/powerpc/bits/fenv.h | |
| parent | 15eca72044d2148b4fe7fe5a0f89ea12a87640fe (diff) | |
| download | glibc-4a59e9adcb9e8475a00ea9088b26b74b48998dd0.tar.gz glibc-4a59e9adcb9e8475a00ea9088b26b74b48998dd0.tar.xz glibc-4a59e9adcb9e8475a00ea9088b26b74b48998dd0.zip | |
2007-04-30 Steven Munroe <sjmunroe@us.ibm.com>
Peter Bergner <bergner@us.ibm.com> * sysdeps/powerpc/bits/fenv.h: Declare __fe_mask_env extern. Define FE_NOMASK_ENV as FE_EANBLED_ENV. Define FE_MASK_ENV. * sysdeps/powerpc/fpu/Makefile: Add fe_mask to libm-support. * sysdeps/powerpc/fpu/fe_mask.c: New file. * sysdeps/powerpc/fpu/fe_nomask.c: Correct comment. * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Call __fe_mask_env() if all FP exceptions disabled. * sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Copy high 32-bits from old FPSCR to new fenv to propagate DFP rounding modes. Call __fe_mask_env() if FP exceptions previously enabled. * sysdeps/powerpc/fpu/fesetenv.c (fesetenv): Change mask to merge exceptions from env. Use __fe_nomask_env() or __fe_mask_env() when transitioning from all exceptions disabled to any exception enabled or visa versa. * sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Change mask to merge exceptions from env. Call __fe_nomask_env or __fe_mask_env when transitioning from all exceptions disabled to any exception enabled or visa versa. * sysdeps/unix/sysv/linux/powerpc/powerpc32/fe_nomask.c: Moved to... * sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/fe_nomask.c: ...here. * sysdeps/unix/sysv/linux/powerpc/powerpc64/fe_nomask.c: Moved to... * sysdeps/unix/sysv/linux/powerpc/powerpc64/fpu/fe_nomask.c: ...here. * sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/fe_mask.c: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/fpu/fe_mask.c: New file.
Diffstat (limited to 'sysdeps/powerpc/bits/fenv.h')
| -rw-r--r-- | sysdeps/powerpc/bits/fenv.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/sysdeps/powerpc/bits/fenv.h b/sysdeps/powerpc/bits/fenv.h index 8509b4b0c3..10582a6ff6 100644 --- a/sysdeps/powerpc/bits/fenv.h +++ b/sysdeps/powerpc/bits/fenv.h @@ -137,9 +137,19 @@ extern const fenv_t __fe_nonieee_env; # define FE_NONIEEE_ENV (&__fe_nonieee_env) /* Floating-point environment with all exceptions enabled. Note that - just evaluating this value will set the processor into 'FPU - exceptions imprecise recoverable' mode, which may cause a significant - performance penalty (but have no other visible effect). */ + just evaluating this value does not change the processor exception mode. + Passing this mask to fesetenv will result in a prctl syscall to change + the MSR FE0/FE1 bits to "Precise Mode". On some processors this will + result in slower floating point execution. This will last until an + fenv or exception mask is installed that disables all FP exceptions. */ extern const fenv_t *__fe_nomask_env (void); -# define FE_NOMASK_ENV (__fe_nomask_env ()) +# define FE_NOMASK_ENV FE_ENABLED_ENV + +/* Floating-point environment with all exceptions disabled. Note that + just evaluating this value does not change the processor exception mode. + Passing this mask to fesetenv will result in a prctl syscall to change + the MSR FE0/FE1 bits to "Ignore Exceptions Mode". On most processors + this allows the fastest possible floating point execution.*/ +extern const fenv_t *__fe_mask_env (void); +# define FE_MASK_ENV FE_DFL_ENV #endif |