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author | Andrew Bennett <andrew.bennett@imgtec.com> | 2015-08-24 22:06:29 +0100 |
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committer | Matthew Fortune <matthew.fortune@imgtec.com> | 2015-09-08 16:52:43 +0100 |
commit | 7498d7676dc9ffb38fcb39635bae7c195740d6f7 (patch) | |
tree | 777b1522f456dde55596ed3388229f57eb6a9dfe /sysdeps/mips | |
parent | 697ed91ca901f8e2ce3ba2b7cf69cdb18c8b37ad (diff) | |
download | glibc-7498d7676dc9ffb38fcb39635bae7c195740d6f7.tar.gz glibc-7498d7676dc9ffb38fcb39635bae7c195740d6f7.tar.xz glibc-7498d7676dc9ffb38fcb39635bae7c195740d6f7.zip |
MIPS: Only use .set mips* assembler directives when necessary
There are a few .set mips* assembler directives used in the MIPS specific sysdep code that force an instruction to be assembled for a specific ISA. The reason for these is to allow an instruction to be encoded when it might not be supported in the current ISA (when the code is run the Linux kernel will trap and emulate any unsupported instructions). Unfortunately forcing a specific ISA means that when assembling for a newer ISA, where the instruction has a different encoding, the wrong encoding will be used. * sysdeps/mips/bits/atomic.h [_MIPS_SIM == _ABIO32] (MIPS_PUSH_MIPS2): Only use .set mips2 if the current ISA is below mips2. * sysdeps/mips/sys/tas.h [_MIPS_SIM == _ABIO32] (_test_and_set): Likewise. * sysdeps/mips/nptl/tls.h (READ_THREAD_POINTER): Only use .set mips32r2 if the current ISA is below mips32r2. * sysdeps/mips/tls-macros.h (TLS_RDHWR): New define. (TLS_IE): Updated to use the TLD_RDHWR macro. (TLS_LE): Likewise. * sysdeps/unix/mips/sysdep.h (__mips_isa_rev): Moved out of #ifdef __ASSEMBLER__ condition.
Diffstat (limited to 'sysdeps/mips')
-rw-r--r-- | sysdeps/mips/bits/atomic.h | 2 | ||||
-rw-r--r-- | sysdeps/mips/nptl/tls.h | 36 | ||||
-rw-r--r-- | sysdeps/mips/sys/tas.h | 2 | ||||
-rw-r--r-- | sysdeps/mips/tls-macros.h | 15 |
4 files changed, 36 insertions, 19 deletions
diff --git a/sysdeps/mips/bits/atomic.h b/sysdeps/mips/bits/atomic.h index a39188160b..375448957c 100644 --- a/sysdeps/mips/bits/atomic.h +++ b/sysdeps/mips/bits/atomic.h @@ -38,7 +38,7 @@ typedef uintptr_t uatomicptr_t; typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; -#if _MIPS_SIM == _ABIO32 +#if _MIPS_SIM == _ABIO32 && __mips < 2 #define MIPS_PUSH_MIPS2 ".set mips2\n\t" #else #define MIPS_PUSH_MIPS2 diff --git a/sysdeps/mips/nptl/tls.h b/sysdeps/mips/nptl/tls.h index ef1145779d..e69c3970df 100644 --- a/sysdeps/mips/nptl/tls.h +++ b/sysdeps/mips/nptl/tls.h @@ -25,6 +25,8 @@ # include <stdbool.h> # include <stddef.h> # include <stdint.h> +/* Get system call information. */ +# include <sysdep.h> /* Type for the dtv. */ typedef union dtv @@ -42,29 +44,37 @@ typedef union dtv # define READ_THREAD_POINTER() (__builtin_thread_pointer ()) #else /* Note: rd must be $v1 to be ABI-conformant. */ -# define READ_THREAD_POINTER() \ - ({ void *__result; \ - asm volatile (".set\tpush\n\t.set\tmips32r2\n\t" \ - "rdhwr\t%0, $29\n\t.set\tpop" : "=v" (__result)); \ - __result; }) +# if __mips_isa_rev >= 2 +# define READ_THREAD_POINTER() \ + ({ void *__result; \ + asm volatile ("rdhwr\t%0, $29" : "=v" (__result)); \ + __result; }) +# else +# define READ_THREAD_POINTER() \ + ({ void *__result; \ + asm volatile (".set\tpush\n\t.set\tmips32r2\n\t" \ + "rdhwr\t%0, $29\n\t.set\tpop" : "=v" (__result)); \ + __result; }) +# endif #endif #else /* __ASSEMBLER__ */ # include <tcb-offsets.h> -# define READ_THREAD_POINTER(rd) \ - .set push; \ - .set mips32r2; \ - rdhwr rd, $29; \ - .set pop +# if __mips_isa_rev >= 2 +# define READ_THREAD_POINTER(rd) rdhwr rd, $29 +# else +# define READ_THREAD_POINTER(rd) \ + .set push; \ + .set mips32r2; \ + rdhwr rd, $29; \ + .set pop +# endif #endif /* __ASSEMBLER__ */ #ifndef __ASSEMBLER__ -/* Get system call information. */ -# include <sysdep.h> - /* The TP points to the start of the thread blocks. */ # define TLS_DTV_AT_TP 1 # define TLS_TCB_AT_TP 0 diff --git a/sysdeps/mips/sys/tas.h b/sysdeps/mips/sys/tas.h index e14b5f04c1..2820ff6f05 100644 --- a/sysdeps/mips/sys/tas.h +++ b/sysdeps/mips/sys/tas.h @@ -41,7 +41,7 @@ __NTH (_test_and_set (int *__p, int __v)) __asm__ __volatile__ ("/* Inline test and set */\n" ".set push\n\t" -#if _MIPS_SIM == _ABIO32 +#if _MIPS_SIM == _ABIO32 && __mips < 2 ".set mips2\n\t" #endif "sync\n\t" diff --git a/sysdeps/mips/tls-macros.h b/sysdeps/mips/tls-macros.h index 3e87e42ea1..a6fdfbc0ad 100644 --- a/sysdeps/mips/tls-macros.h +++ b/sysdeps/mips/tls-macros.h @@ -2,6 +2,7 @@ #include <sys/cdefs.h> #include <sys/asm.h> +#include <sysdep.h> #define __STRING2(X) __STRING(X) #define ADDU __STRING2(PTR_ADDU) @@ -38,6 +39,14 @@ # define UNLOAD_GP #endif +# if __mips_isa_rev >= 2 +# define TLS_RDHWR "rdhwr\t%0,$29" +# else +# define TLS_RDHWR \ + ".set push\n\t.set mips32r2\n\t" \ + "rdhwr\t%0,$29\n\t.set pop" +#endif + #ifndef __mips16 # define TLS_GD(x) \ ({ void *__result, *__tmp; \ @@ -60,8 +69,7 @@ __result; }) # define TLS_IE(x) \ ({ void *__result, *__tmp; \ - asm (".set push\n\t.set mips32r2\n\t" \ - "rdhwr\t%0,$29\n\t.set pop" \ + asm (TLS_RDHWR \ : "=v" (__result)); \ asm (LOAD_GP LW " $3,%%gottprel(" #x ")($28)\n\t" \ ADDU " %0,%0,$3" \ @@ -71,8 +79,7 @@ __result; }) # define TLS_LE(x) \ ({ void *__result; \ - asm (".set push\n\t.set mips32r2\n\t" \ - "rdhwr\t%0,$29\n\t.set pop" \ + asm (TLS_RDHWR \ : "=v" (__result)); \ asm ("lui $3,%%tprel_hi(" #x ")\n\t" \ "addiu $3,$3,%%tprel_lo(" #x ")\n\t" \ |