Update

2002-09-10  Hartvig Ekner  <hartvige@mips.com>

	* sysdeps/mips/memcpy.S: New file.
	* sysdeps/mips/memset.S: New file.
	* sysdeps/mips/fpu/e_sqrt.c:  New file.
	* sysdeps/mips/fpu/e_sqrtf.c: New file.

	* fpu/fclrexcpt.c: Cleaned up the FPU exception stuff - was not
	functional before. Also removed all SHLIB_COMPAT stuff.
	* fpu/fegetenv.c: Likewise.
	* fpu/fesetenv.c:: Likewise.
	* fpu/feupdateenv.c: Likewise.
	* fpu/fgetexcptflg.c: Likewise.
	* fpu/fraiseexcpt.c: Likewise.

	* sysdeps/mips/fpu/fsetexcptflg.c: New file.

1 files changed, 3 insertions, 10 deletions

diff --git a/sysdeps/mips/fpu/fclrexcpt.c b/sysdeps/mips/fpu/fclrexcpt.c
index 2c35047a8c..f773312b34 100644
--- a/sysdeps/mips/fpu/fclrexcpt.c
+++ b/sysdeps/mips/fpu/fclrexcpt.c
@@ -21,10 +21,9 @@
 #include <fenv.h>
 #include <fenv_libc.h>
 #include <fpu_control.h>
-#include <shlib-compat.h>
 
 int
-__feclearexcept (int excepts)
+feclearexcept (int excepts)
 {
   int cw;
 
@@ -35,8 +34,8 @@ __feclearexcept (int excepts)
   _FPU_GETCW (cw);
 
   /* Clear exception flag bits and cause bits. If the cause bit is not
-     cleared, the next CTC instruction (just below) will re-generate
-     the exception.  */
+     cleared, the next CTC instruction (just below) will re-generate the
+     exception.  */
 
   cw &= ~(excepts | (excepts << CAUSE_SHIFT));
 
@@ -46,9 +45,3 @@ __feclearexcept (int excepts)
   /* Success.  */
   return 0;
 }
-
-#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2)
-strong_alias (__feclearexcept, __old_feclearexcept)
-compat_symbol (libm, __old_feclearexcept, feclearexcept, GLIBC_2_1);
-#endif
-versioned_symbol (libm, __feclearexcept, feclearexcept, GLIBC_2_2);