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| author | H.J. Lu <hjl.tools@gmail.com> | 2017-04-07 07:44:40 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2017-04-07 07:44:59 -0700 |
| commit | bf7730194fed694a9ce821c306683266a5a7b78b (patch) | |
| tree | cd77906b47ae361b8cbd50950a5f58e08277e1dd /sysdeps/i386/fpu/feholdexcpt.c | |
| parent | 893ba3eac9b07d0d5feac232c551af0e163f939c (diff) | |
| download | glibc-bf7730194fed694a9ce821c306683266a5a7b78b.tar.gz glibc-bf7730194fed694a9ce821c306683266a5a7b78b.tar.xz glibc-bf7730194fed694a9ce821c306683266a5a7b78b.zip | |
Check if SSE is available with HAS_CPU_FEATURE
Similar to other CPU feature checks, check if SSE is available with HAS_CPU_FEATURE. * sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use HAS_CPU_FEATURE to check for SSE. * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise. * sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise. * sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise. * sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise. * sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise. * sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise. * sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise. * sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise. * sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise. * sysdeps/i386/setfpucw.c (__setfpucw): Likewise. * sysdeps/x86/cpu-features.h (bit_cpu_SSE): New. (index_cpu_SSE): Likewise. (reg_SSE): Likewise.
Diffstat (limited to 'sysdeps/i386/fpu/feholdexcpt.c')
| -rw-r--r-- | sysdeps/i386/fpu/feholdexcpt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/i386/fpu/feholdexcpt.c b/sysdeps/i386/fpu/feholdexcpt.c index cce883c792..d327358913 100644 --- a/sysdeps/i386/fpu/feholdexcpt.c +++ b/sysdeps/i386/fpu/feholdexcpt.c @@ -30,7 +30,7 @@ __feholdexcept (fenv_t *envp) __asm__ volatile ("fnstenv %0; fnclex" : "=m" (*envp)); /* If the CPU supports SSE we set the MXCSR as well. */ - if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0) + if (HAS_CPU_FEATURE (SSE)) { unsigned int xwork; |