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authorCarlos O'Donell <carlos@systemhalted.org>2015-03-11 02:42:27 -0400
committerCarlos O'Donell <carlos@systemhalted.org>2015-03-11 02:48:59 -0400
commite4363cfb5760d88a9f353c69383b15d5c2705070 (patch)
treed45136a41ea523d4ee293b62fcbe98b2095a16d6 /sysdeps/hppa/fpu/fpu_control.h
parentfae1aa8d226ce860124efd67ede03004b19b89e2 (diff)
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hppa: Fix feupdateenv and fesetexceptflag (Bug 18111).
The function feupdateenv has been fixed to correctly handle FE_DFL_ENV
and FE_NOMASK_ENV.

The fesetexceptflag function has been fixed to correctly handle setting
the new flags instead of just OR-ing the existing flags.

This fixes the test-fenv-return and test-fenvinline failures on hppa.
Diffstat (limited to 'sysdeps/hppa/fpu/fpu_control.h')
-rw-r--r--sysdeps/hppa/fpu/fpu_control.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/sysdeps/hppa/fpu/fpu_control.h b/sysdeps/hppa/fpu/fpu_control.h
index ba9692fe63..2087928496 100644
--- a/sysdeps/hppa/fpu/fpu_control.h
+++ b/sysdeps/hppa/fpu/fpu_control.h
@@ -19,7 +19,7 @@
 #ifndef _FPU_CONTROL_H
 #define _FPU_CONTROL_H
 
-/* Masking of interrupts */
+/* Masking of interrupts.  */
 #define _FPU_MASK_PM	0x00000001	/* Inexact (I) */
 #define _FPU_MASK_UM	0x00000002	/* Underflow (U) */
 #define _FPU_MASK_OM	0x00000004	/* Overflow (O) */
@@ -30,6 +30,8 @@
 #define _FPU_HPPA_MASK_RM	0x00000600	/* Rounding mode mask */
 /* Masking of interrupt enable bits.  */
 #define _FPU_HPPA_MASK_INT	0x0000001f	/* Interrupt mask */
+/* Shift by 27 to install flag bits.  */
+#define _FPU_HPPA_SHIFT_FLAGS	27
 
 /* There are no reserved bits in the PA fpsr (though some are undefined).  */
 #define _FPU_RESERVED	0x00000000
@@ -55,6 +57,9 @@ typedef unsigned int fpu_control_t;
 #define _FPU_SETCW(cw) \
 ({										\
   union { __extension__ unsigned long long __fpreg; unsigned int __halfreg[2]; } __fullfp;	\
+  /* Get the current status word and set the control word.  */			\
+  __asm__ ("fstd %%fr0,0(%1)\n\t"						\
+	   : "=m" (__fullfp.__fpreg) : "r" (&__fullfp.__fpreg) : "%r0");	\
   __fullfp.__halfreg[0] = cw;							\
   __asm__ ("fldd 0(%1),%%fr0\n\t"						\
 	   : : "m" (__fullfp.__fpreg), "r" (&__fullfp.__fpreg) : "%r0" );	\