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authorWilco <wdijkstr@arm.com>2014-06-24 12:04:27 +0000
committerWilco <wdijkstr@arm.com>2014-06-24 12:04:27 +0000
commit001f7b773c637560ecfa686452a5e68d60d07db3 (patch)
tree08bd670c6b892304a287c56f6cbeb00e92276567 /sysdeps/arm/fedisblxcpt.c
parent4841e6a6c2fa691201fb52dfaf6b6a8920229bac (diff)
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Speed up the ARM fenv implementation by avoiding unnecessary FPSCR
writes if the FPSCR remains unchanged.

2014-06-24  Wilco  <wdijkstr@arm.com>

	* sysdeps/arm/fclrexcpt.c (feclearexcept):
	Optimize to avoid unnecessary FPSCR writes.
	* sysdeps/arm/fedisblxcpt.c (fedisableexcept): Likewise.
	* sysdeps/arm/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/arm/fsetexcptflg.c (fesetexceptflag): Likewise.
	* sysdeps/arm/setfpucw.c (__setfpucw): Likewise.
Diffstat (limited to 'sysdeps/arm/fedisblxcpt.c')
-rw-r--r--sysdeps/arm/fedisblxcpt.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/sysdeps/arm/fedisblxcpt.c b/sysdeps/arm/fedisblxcpt.c
index f2956cd32a..d5e0f0031a 100644
--- a/sysdeps/arm/fedisblxcpt.c
+++ b/sysdeps/arm/fedisblxcpt.c
@@ -35,7 +35,9 @@ fedisableexcept (int excepts)
   excepts &= FE_ALL_EXCEPT;
   new_fpscr = fpscr & ~(excepts << FE_EXCEPT_SHIFT);
 
-  _FPU_SETCW (new_fpscr);
+  /* Write new exceptions if changed.  */
+  if (new_fpscr != fpscr)
+    _FPU_SETCW (new_fpscr);
 
   return (fpscr >> FE_EXCEPT_SHIFT) & FE_ALL_EXCEPT;
 }