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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-04-16 08:18:23 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-04-16 17:24:31 -0300 |
| commit | 743b9c2a98426fb40f8ffee3529c8870bc5300f5 (patch) | |
| tree | f050338793677c5b1b2cd681d40c80a1be44ab08 /sysdeps/arm/armv7 | |
| parent | 326e74e7c18ab12ac8e4b67cce295d32fcc1cf68 (diff) | |
| download | glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.tar.gz glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.tar.xz glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.zip | |
arm: Remove ununsed ARM code in optimized implementation
This patch removes the ununsed ARM code path for armv6t2 memchr and strlen and armv7 memch and strcmp. In all implementation, the ARM code is not used in any possible build (unless glibc is explicit build with the non-documented NO_THUMB compiler flag) and for armv7 the resulting code either produces wrong results (memchr) and throw build error (strcmp). Checked on arm-linux-gnueabihf built targeting both armv6 and armv7. * sysdeps/arm/armv6t2/memchr.S (memchr): Remove ARM code path. * sysdeps/arm/armv6t2/strlen.S (memchr): Likewise. * sysdeps/arm/armv7/multiarch/memchr_neon.S (memchr): Likewise. * sysdeps/arm/armv7/strcmp.S (strcmp): Likewise.
Diffstat (limited to 'sysdeps/arm/armv7')
| -rw-r--r-- | sysdeps/arm/armv7/multiarch/memchr_neon.S | 16 | ||||
| -rw-r--r-- | sysdeps/arm/armv7/strcmp.S | 23 |
2 files changed, 0 insertions, 39 deletions
diff --git a/sysdeps/arm/armv7/multiarch/memchr_neon.S b/sysdeps/arm/armv7/multiarch/memchr_neon.S index 1b2ae75aa0..6fbf9b8898 100644 --- a/sysdeps/arm/armv7/multiarch/memchr_neon.S +++ b/sysdeps/arm/armv7/multiarch/memchr_neon.S @@ -68,11 +68,7 @@ * allows to identify exactly which byte has matched. */ -#ifndef NO_THUMB .thumb_func -#else - .arm -#endif .p2align 4,,15 ENTRY(memchr) @@ -132,12 +128,7 @@ ENTRY(memchr) /* The first block can also be the last */ bls .Lmasklast /* Have we found something already? */ -#ifndef NO_THUMB cbnz synd, .Ltail -#else - cmp synd, #0 - bne .Ltail -#endif .Lloopintro: @@ -176,16 +167,9 @@ ENTRY(memchr) vpadd.i8 vdata0_0, vdata0_0, vdata1_0 vpadd.i8 vdata0_0, vdata0_0, vdata0_0 vmov synd, vdata0_0[0] -#ifndef NO_THUMB cbz synd, .Lnotfound bhi .Ltail /* Uses the condition code from subs cntin, cntin, #32 above. */ -#else - cmp synd, #0 - beq .Lnotfound - cmp cntin, #0 - bhi .Ltail -#endif .Lmasklast: diff --git a/sysdeps/arm/armv7/strcmp.S b/sysdeps/arm/armv7/strcmp.S index 060b865658..2626fdf72e 100644 --- a/sysdeps/arm/armv7/strcmp.S +++ b/sysdeps/arm/armv7/strcmp.S @@ -83,8 +83,6 @@ #define syndrome tmp2 -#ifndef NO_THUMB -/* This code is best on Thumb. */ .thumb /* In Thumb code we can't use MVN with a register shift, but we do have ORN. */ @@ -94,27 +92,6 @@ .macro apply_mask data_reg, mask_reg orn \data_reg, \data_reg, \mask_reg .endm -#else -/* In ARM code we don't have ORN, but we can use MVN with a register shift. */ -.macro prepare_mask mask_reg, nbits_reg - mvn \mask_reg, const_m1, S2HI \nbits_reg -.endm -.macro apply_mask data_reg, mask_reg - orr \data_reg, \data_reg, \mask_reg -.endm - -/* These clobber the condition codes, which the real Thumb cbz/cbnz - instructions do not. But it doesn't matter for any of the uses here. */ -.macro cbz reg, label - cmp \reg, #0 - beq \label -.endm -.macro cbnz reg, label - cmp \reg, #0 - bne \label -.endm -#endif - /* Macro to compute and return the result value for word-aligned cases. */ |