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| author | Kito Cheng <kito.cheng@sifive.com> | 2022-06-28 21:52:19 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-06-30 08:04:52 -0700 |
| commit | c22d2021a9f9bdea62398976eea4f0e6ef668b7d (patch) | |
| tree | 31c84de370e090ad007b11e4d679a5eff94ab717 /signal | |
| parent | e9dd3682963a7038d699430e3ece68045b6caafc (diff) | |
| download | glibc-c22d2021a9f9bdea62398976eea4f0e6ef668b7d.tar.gz glibc-c22d2021a9f9bdea62398976eea4f0e6ef668b7d.tar.xz glibc-c22d2021a9f9bdea62398976eea4f0e6ef668b7d.zip | |
riscv: Use memcpy to handle unaligned access when fixing R_RISCV_RELATIVE
Although RISC-V Linux will enable the unaligned memory access handler by default, that is quite expensive in general, using memcpy will be much cheaper - just break down that into several load/store byte instructions. ARM and MIPS has similar issue: ARM: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51456 MIPS: https://gcc.gnu.org/legacy-ml/gcc-help/2005-07/msg00325.html Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Diffstat (limited to 'signal')
0 files changed, 0 insertions, 0 deletions