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author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-11-02 10:56:00 +0100 |
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committer | Florian Weimer <fweimer@redhat.com> | 2018-11-02 10:56:00 +0100 |
commit | 65010329f2c596bdd1204c1c9c9baac0193637af (patch) | |
tree | c274a78baebd4917b7c103434c94c169ff88eb6f /resolv/gai_misc.c | |
parent | e1af1df694603c0dcd5118c30eea2cdeb01a1a0b (diff) | |
download | glibc-65010329f2c596bdd1204c1c9c9baac0193637af.tar.gz glibc-65010329f2c596bdd1204c1c9c9baac0193637af.tar.xz glibc-65010329f2c596bdd1204c1c9c9baac0193637af.zip |
x86: Fix Haswell CPU string flags (BZ#23709)
Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the default flags for Haswell models. Previously, new models were handled by the default switch path, which assumed a Core i3/i5/i7 if AVX is available. After the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and Prefer_PMINUB_for_stringop (only the TSX one). This patch fixes it by disentangle the TSX flag handling from the memory optimization ones. The strstr case cited on patch now selects the __strstr_sse2_unaligned as expected for the Haswell cpu. Checked on x86_64-linux-gnu. [BZ #23709] * sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits independently of other flags. (cherry picked from commit c3d8dc45c9df199b8334599a6cbd98c9950dba62)
Diffstat (limited to 'resolv/gai_misc.c')
0 files changed, 0 insertions, 0 deletions