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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2020-08-28 17:51:40 +0100 |
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| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2020-10-14 15:57:02 +0100 |
| commit | d0a5b769027b17a7000ebc58e240ddd98ae0d719 (patch) | |
| tree | cf726b48d7c9206fc6463e2e788d06c1f900c312 /posix | |
| parent | 24a30c595958a1b23b620bc3dea62b0ab9d8f480 (diff) | |
| download | glibc-d0a5b769027b17a7000ebc58e240ddd98ae0d719.tar.gz glibc-d0a5b769027b17a7000ebc58e240ddd98ae0d719.tar.xz glibc-d0a5b769027b17a7000ebc58e240ddd98ae0d719.zip | |
AArch64: Improve backwards memmove performance
On some microarchitectures performance of the backwards memmove improves if the stores use STR with decreasing addresses. So change the memmove loop in memcpy_advsimd.S to use 2x STR rather than STP. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> (cherry picked from commit bd394d131c10c9ec22c6424197b79410042eed99)
Diffstat (limited to 'posix')
0 files changed, 0 insertions, 0 deletions