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authorChris Metcalf <cmetcalf@tilera.com>2012-09-24 16:03:33 -0400
committerChris Metcalf <cmetcalf@tilera.com>2012-09-24 16:03:33 -0400
commit27ed6484ecc852cf9a85a4e9202c6f63b8bcd568 (patch)
tree72077664543f7f3b80f4c10facb81847a3ecc909 /ports
parent189e935bf8d51688e28f4271ca91b5c6f6ce629c (diff)
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tile: fix two comments that said "tile" to properly say "tilepro"
Diffstat (limited to 'ports')
-rw-r--r--ports/sysdeps/tile/sysdep.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/ports/sysdeps/tile/sysdep.h b/ports/sysdeps/tile/sysdep.h
index 4f27cb2bed..4db70836e4 100644
--- a/ports/sysdeps/tile/sysdep.h
+++ b/ports/sysdeps/tile/sysdep.h
@@ -66,7 +66,7 @@
 #define REGSIZE		4
 #endif
 
-/* Support a limited form of shared assembly between tile and tilegx.
+/* Support a limited form of shared assembly between tilepro and tilegx.
    The presumption is that LD/ST are used for manipulating registers.
    Since opcode parsing is case-insensitive, we don't need to provide
    definitions for these on tilegx.  */
@@ -86,7 +86,7 @@
 #endif
 
 /* Provide "pointer-oriented" instruction variants.  These differ not
-   just for tile vs tilegx, but also for tilegx -m64 vs -m32.  */
+   just for tilepro vs tilegx, but also for tilegx -m64 vs -m32.  */
 #if defined __tilegx__ && __WORDSIZE == 32
 #define ADD_PTR		addx
 #define ADDI_PTR	addxi