MIPS: Correct the handling of reserved FCSR bits

Reserved bits in the Floating-Point Control and Status Register (FCSR)
should not be implicitly cleared by fedisableexcept or feenableexcept,
there is no reason to.  Among these are the 8 condition codes and one of
the two bits reserved for architecture implementers (bits #22 & #21).

As to the latter, there is no reason to treat any of them as reserved
either, they should be user controllable and settable via __fpu_control
override as the user sees fit.  For example in processors implemented by
MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to
change the treatment of denormalised operands and tiny results: bit #22
is Flush Override (FO) and bit #21 is Flush to Nearest (FN).  They cause
non-IEEE-compliant behaviour, but some programs may have a use for such
modes of operation; the library should not obstruct such use just as it
does not for the architectural Flush to Zero (FS) bit (bit #24).

Therefore the change adjusts the reserved mask accordingly and also
documents the distinction between bits 22:21 and 20:18.

2 files changed, 0 insertions, 2 deletions

diff --git a/ports/sysdeps/mips/fpu/fedisblxcpt.c b/ports/sysdeps/mips/fpu/fedisblxcpt.c
index 1db197f213..7498c0c27c 100644
--- a/ports/sysdeps/mips/fpu/fedisblxcpt.c
+++ b/ports/sysdeps/mips/fpu/fedisblxcpt.c
@@ -34,7 +34,6 @@ fedisableexcept (int excepts)
   excepts &= FE_ALL_EXCEPT;
 
   new_exc &= ~(excepts << ENABLE_SHIFT);
-  new_exc &= ~_FPU_RESERVED;
   _FPU_SETCW (new_exc);
 
   return old_exc;
diff --git a/ports/sysdeps/mips/fpu/feenablxcpt.c b/ports/sysdeps/mips/fpu/feenablxcpt.c
index 2a3a07618d..bca8e3d23e 100644
--- a/ports/sysdeps/mips/fpu/feenablxcpt.c
+++ b/ports/sysdeps/mips/fpu/feenablxcpt.c
@@ -34,7 +34,6 @@ feenableexcept (int excepts)
   excepts &= FE_ALL_EXCEPT;
 
   new_exc |= excepts << ENABLE_SHIFT;
-  new_exc &= ~_FPU_RESERVED;
   _FPU_SETCW (new_exc);
 
   return old_exc;